CURRENT FEATURE ARTICLES

Ten-Step Program
Sequence PowerArtist Identifies Ways to Reduce Power (Bryon Moyer)
Three Chords and the Truth
Aart de Geus and Synopsys go Quick to Four
(Kevin Morris)
Avoiding Failure Analysis Paralysis
Cadence Describes the DFM-Diagnostics Link
(Bryon Moyer)
Almost Instant Replay
Mentor Announces Codelink for Debugging Processor-Driven Tests (Bryon Moyer)
The Spirit of Standardization
IP Re-use Takes Center Stage (Kevin Morris)
Accommodating Change
Cadence Announces a Front-End ECO Tool
(Bryon Moyer)

JOURNAL WEBCASTS

NEW!! CHALK TALK Creating Secure Mobile Devices With Open Kernel Labs OKL4. In this Chalk Talk, Amelia Dalton delves into the world of software security and microkernels in mobile devices with Gernot Heiser and Rob McCammon of Open Kernel Labs. (Open Kernel Labs)

CHALK TALK Low Power Design With Xilinx and Linear Technology. Join Amelia Dalton as she chats with Mark Moran of Xilinx and Afshin Odabaee of Linear Technology about low power FPGA based designs. (Xilinx)

CHALK TALK Designing Embedded Systems With Linux and low cost FPGAs. Join Amelia Dalton as she chats with industry experts about simplifying embedded systems design with Linux running on low-cost programmable system-on-chip platforms. (Xilinx)

CHALK TALK Lowest Total System Cost With Xilinx
Spartan-3. Amelia Dalton chats with Mark Moran of Xilinx about reducing your overall system cost with Xilinx Spartan-3 family of FPGAs (Xilinx)

CHALK TALK Low Cost FPGA with Serdes Lattice ECP2M. Amelia Dalton talks with Bertrand Leigh of Lattice Semiconductor about low-cost FPGAs with multi-gigabit SerDes interface capability. (Lattice Semiconductor)

CHALK TALK Crossing the Gap between Algorithm and Hardware Implementation. Join Amelia Dalton as she learns how C++ and Catapult C Synthesis can accelerate the design, implementation, and verification of complex system-level algorithms. (Mentor Graphics)

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Ten-Step Program
Sequence PowerArtist Identifies Ways to Reduce Power (Bryon Moyer)

Power has become a key design consideration for SoCs in pretty much any application. We’ve looked at some ways of reducing power in past articles, largely at a high level. We continue here with a specific look at some techniques that can be identified by a new tool from Sequence called PowerArtist. This tool takes ten specific steps to identify ways to reduce power, although only a couple of them are automatically implemented. Most of them may take some engineering evaluation to decide whether to implement, and, if so, exactly how to do them, so those techniques are so-called “guided” ones, in that the tool guides the engineer towards power savings opportunities.

The focus of the power savings techniques was directed by some data that Sequence gathered regarding where power is typically consumed in an SoC. The top three items were the clocks (30-60%), memories (20-50%), and datapath (~20%). These are therefore the areas that PowerArtist considers. Four of its “PowerBots” – the name they use for each of the analysis engines – address clock power; three address memories, and three cover the datapath.

When it comes to clocks, it’s all about the enables. It is generally accepted that using clock enables can reduce power. What’s less well understood is that for active signals that would rarely be disabled, adding a clock enable can actually increase power, since the power added by additional enabling circuitry overwhelms any potential minor power reduction. So a key aspect of what PowerArtist does is to determine which clocks would actually benefit from having a clock enable.

Of course, simply adding gating to a clock signal may disrupt the timing of that clock and certainly will add skew and unbalance the clock tree. Synthesis engines already have the capability of recognizing certain styles of logic as opportunities for clock gating and can implement the gating, taking into account all of the timing considerations. [more]