CURRENT FEATURE ARTICLES

Avoiding Failure Analysis Paralysis
Cadence Describes the DFM-Diagnostics Link
(Bryon Moyer)
Almost Instant Replay
Mentor Announces Codelink for Debugging Processor-Driven Tests (Bryon Moyer)
The Spirit of Standardization
IP Re-use Takes Center Stage (Kevin Morris)
Accommodating Change
Cadence Announces a Front-End ECO Tool
(Bryon Moyer)
Making Quality Everyone’s Business
A Quick Look at isQED (Bryon Moyer)
Methods for Reducing Marketing Jitter Through Filtering of Marketing Noise in Conference Presentations (Bryon Moyer)

JOURNAL WEBCASTS

NEW!! CHALK TALK Designing Embedded Systems With Linux and low cost FPGAs. Join Amelia Dalton as she chats with industry experts about simplifying embedded systems design with Linux running on low-cost programmable system-on-chip platforms. (Xilinx)

CHALK TALK Lowest Total System Cost With Xilinx
Spartan-3. Amelia Dalton chats with Mark Moran of Xilinx about reducing your overall system cost with Xilinx Spartan-3 family of FPGAs (Xilinx)

CHALK TALK Low Cost FPGA with Serdes Lattice ECP2M. Amelia Dalton talks with Bertrand Leigh of Lattice Semiconductor about low-cost FPGAs with multi-gigabit SerDes interface capability. (Lattice Semiconductor)

CHALK TALK Crossing the Gap between Algorithm and Hardware Implementation. Join Amelia Dalton as she learns how C++ and Catapult C Synthesis can accelerate the design, implementation, and verification of complex system-level algorithms. (Mentor Graphics)

Approaching Yield in the Nanometer Age - DFM Methodology. As we dive deeper into the nanometer era, we must rethink the way we design. Tools, techniques, and methods that once worked without fail cannot hold up at the 65 and 45 nm depths, making it more challenging than ever to achieve yield. This tutorial explores these challenges within both the business and historical context of the IC design and manufacturing process. (Mentor Graphics)

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Avoiding Failure Analysis Paralysis
Cadence Describes the DFM-Diagnostics Link (Bryon Moyer)

Back when I was a product engineer working on bipolar PALs (oops – I mean, PAL® devices), one of my main activities was figuring out what was wrong. That was most of the job of a product engineer: fix what’s broken. You don’t spend any time working on the stuff that’s working, you work on what isn’t working. Assuming it’s a chip that’s wrong, the process would typically start with a trip into the testing area to put a part on the tester and datalog it to see some evidence of things going awry. Armed with that, the next job was to spread a big schematic out on a table and start looking at the circuits, figuring out what could be causing the problem. You’d come up with a couple scenarios, and next you’d have to look in the actual chip.

Of course, in order to look at the chip, we had to spread a big layout sheet on a table to trace out where the circuits were physically located. Then we’d know where to look. The chip would have to be decapped – I could do that myself if it was a CERDIP (ceramic packaging, where you could pop off the top); otherwise you needed to go to one of those scary guys that knew just a bit too much about chemistry (and whom you wanted to keep happy with occasional gifts of jerky or sunflower seeds) to have a hole etched in the plastic. Hopefully that was enough, and then you could go into the lab and use microscopes and microprobes and oscilloscopes and such to poke through dielectric layers, perhaps cut a metal line to get to something below, and with any luck you’d identify a problem that could be fixed. In the worst case you had to go back to Scary Guy for more delayering, or perhaps a SEM session. Or – yikes – chemical analysis. It was all seat-of-the-pants, using forensic techniques worthy of CSI – Jurassic Edition, and you let your data and observations tell you what the next step should be.

Unfortunately, a few things have changed to complicate this serene pastoral picture of the past. Start with, oh, about a thousand more pins on the chip. Shrink the features way down, and multiply the number of transistors by, oh, say, a lot. Throw on a few extra layers of metal for good measure, and, well, you gotcherself a problem. [more]