CURRENT FEATURE ARTICLES

The Spirit of Standardization
IP Re-use Takes Center Stage (Kevin Morris)
Accommodating Change
Cadence Announces a Front-End ECO Tool
(Bryon Moyer)
Making Quality Everyone’s Business
A Quick Look at isQED (Bryon Moyer)
Methods for Reducing Marketing Jitter Through Filtering of Marketing Noise in Conference Presentations (Bryon Moyer)
Attacking Abuses of Power - Part 2
(Bryon Moyer)
ISSCC Processor Fest
(Bryon Moyer)
Bigger and Better Storage
(Bryon Moyer)

JOURNAL WEBCASTS

CHALK TALK Low Cost FPGA with Serdes Lattice ECP2M. Amelia Dalton talks with Bertrand Leigh of Lattice Semiconductor about low-cost FPGAs with multi-gigabit SerDes interface capability. (Lattice Semiconductor)

CHALK TALK Crossing the Gap between Algorithm and Hardware Implementation. Join Amelia Dalton as she learns how C++ and Catapult C Synthesis can accelerate the design, implementation, and verification of complex system-level algorithms. (Mentor Graphics)

Approaching Yield in the Nanometer Age - DFM Methodology. As we dive deeper into the nanometer era, we must rethink the way we design. Tools, techniques, and methods that once worked without fail cannot hold up at the 65 and 45 nm depths, making it more challenging than ever to achieve yield. This tutorial explores these challenges within both the business and historical context of the IC design and manufacturing process. (Mentor Graphics)

CHALK TALK Accelerate SoC and ASIC Verification Using FPGA Prototypes. Join Amelia Dalton as she explores methods of ASIC verification available today and why FPGA-based prototypes offer the most affordable and most powerful solution. (Synplicity)

CHALK TALK Advancing SoC Verification Methods.
Join Amelia Dalton as she talks with experts from Mentor Graphics on processor-driven test and other techniques for solving your system-on-chip verification problems. (Mentor Graphics)

The Spirit of Standardization
IP Re-use Takes Center Stage
(Kevin Morris)

Edgar was seldom in the office – even before the current trends in telecommuting and working from home exploded.  He’d waltz through the cube aisles looking important at least once or twice per week – tossing a gigantic notebook with DRAFT stamped on the top onto the desk of some unsuspecting victim.  The target would immediately activate his defenses – talking about how he was behind on his part of the project and was almost critical path right now.  Edgar wasn’t fazed.  Sure, reviewing this draft of the spec might impact this one project at this one company – but Edgar was in this for the Greater Good.  Edgar was a big picture guy – no, more than that.  Edgar was a chronic career committee member.

Every engineering organization has at least one Edgar – the engineer that volunteers for every consortium and “working group” that comes along.  Most of these efforts will go nowhere – and that’s just the way Edgar likes it.  Specifications will be reviewed and modified in perpetuity. Power struggles will ensue amongst idealistically opposing factions debating semantics of corner cases that no real-world scenario will ever see, and corporate one-upsmen will work to be sure that nothing happens that will compromise competitive advantage or benefit a rival.  However, the boondoggle bonanzas that are associated with most of these ill-fated standardization efforts keep the Edgars of the world coming back for more – perhaps even dragging their feet a bit in order to maximize the meals, airfares, and hotel stays consumed on expense account, all while conveniently avoiding most of the real work back at the ranch.

Occasionally, however, we need some of these efforts to accomplish something that will actually benefit the industry.  When it comes to SoC design, nothing is more important in enabling productivity, reducing risk, and simplifying verification than the use of standardized, pre-engineered, proven IP blocks and subsystems.  Unfortunately, with IP coming from a wide variety of sources – many of whom are highly competitive and proprietary, the idea of standardization hasn’t caught on too quickly.  Events like the recent demise of even well-conceived operations like the VSI Alliance (VSIA) take hope down another notch still.  Last July, VSIA announced it was closing down, making provisions for its existing standards to be taken over and consolidated by other industry organizations.

There are, however, a couple of stand-out efforts that apparently our dear Edgar missed out on.  These bodies have actually produced standards that companies are adopting and that engineering teams are using productively in SoC design.  IP-XACT is a standard from The SPIRIT Consortium that enables complex IP from disparate sources to be easily incorporated into a wide variety of SoC designs and design tool flows.  In order for IP to be realistically used and re-used, it needs to be compatible with a variety of design tools and design flows from the major EDA vendors.  The key to the success of IP-XACT may be its generator-centric architecture.  Because of this architecture, tool vendors can extract and optimize the information needed by their particular applications without re-architecting their tools to support a new standard natively.  [more]