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Making Quality Everyone’s Business
A Quick Look at isQED (Bryon Moyer)
Nestled amongst the big noisy conventions like CES, ISSCC, and DAC can be found some more modest, highly focused conferences. These shows may cast a smaller shadow, but they may also benefit from the lack of attendant hoopla, since marketing pays less attention and engineers can focus on the business at hand. One such show that just took place was isQED, or the International Symposium on Quality Electronics Design. Now in its ninth year, isQED focuses on the interactions between design, test, quality, and manufacturing disciplines in the effort to improve such aspects as yield, quality, and robustness.
The technical sessions were dominated by university presentations and were highly focused. Sharing time with these were a number of higher-level industry presentations that were clearly trying to tread a fine line between presenting a topic of general relevance and featuring the companies’ products. Somewhat surprisingly, Microsoft was the first up. This isn’t a company that one usually expects to see at a smallish conference focused on semiconductors. But from their presentation it’s clear that they’re looking to develop a unified collaboration platform to bring together all aspects of system design and sales, including engineering (of course), manufacturing, marketing, field personnel, and even customers (via appropriate firewalls, presumably). Whether they’re able to leverage success in this market remains to be seen, but it appears that, one way or another, they plan to make some noise.
Robert Hum, Mentor’s VP and GM of Design Verification and Test, discussed verification issues, honing in on the challenges of identifying failure modes and applying that information back to design. Physical failure analysis (PFA) is expensive and time consuming. Given a number of failures and the huge number of possible failure modes, just trying to jump into PFA may not be productive. He discussed an automated methodology involving datalogging failures, amassing the results of large numbers of datalogs to identify and Pareto trends along with modeled failure modes, and then using that information to decide what to send into PFA and where to look in order to zero in on the failure mode more quickly.
Cadence’s VP and GM of their test business unit, Sanjiv Taneja, focused on test and the increasing awareness that Design For Test (DFT) strategies need regarding such issues as power and physical layout. In fact, he used the phrase Design With Test, implying that such design elements as scan insertion should feature more prominently as bona fide design issues rather than being an afterthought once the design is basically done. Test pattern generation can also have an impact on power – poorly-generated vectors may draw too much power based on nonsensical switching in “don’t-care” signals, and this power could cause good chips to fail. Vectors also need to take into account some of the newer power infrastructure elements like retention registers and level shifters. [more]
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