CURRENT FEATURE ARTICLES

Methods for Reducing Marketing Jitter Through Filtering of Marketing Noise in Conference Presentations
(Bryon Moyer)
Attacking Abuses of Power - Part 2
(Bryon Moyer)
ISSCC Processor Fest
(Bryon Moyer)
Bigger and Better Storage
(Bryon Moyer)
When Being One-Dimensional Is A Good Thing
Tela Innovations Announces Their Approach to Advanced Cell Layout (Bryon Moyer)
Migrating Complex Networking ASIC Verification Environment to SystemC and SystemVerilog
by Srinath Atluri, Nimalan Siva, and Anant Sakharkar (Cisco) and Rebecca Lipon (Synopsys)

JOURNAL WEBCASTS

NEW!! CHALK TALK Low Cost FPGA with Serdes Lattice ECP2M. Amelia Dalton talks with Bertrand Leigh of Lattice Semiconductor about low-cost FPGAs with multi-gigabit SerDes interface capability. (Lattice Semiconductor)

CHALK TALK Crossing the Gap between Algorithm and Hardware Implementation. Join Amelia Dalton as she learns how C++ and Catapult C Synthesis can accelerate the design, implementation, and verification of complex system-level algorithms. (Mentor Graphics)

Approaching Yield in the Nanometer Age - DFM Methodology. As we dive deeper into the nanometer era, we must rethink the way we design. Tools, techniques, and methods that once worked without fail cannot hold up at the 65 and 45 nm depths, making it more challenging than ever to achieve yield. This tutorial explores these challenges within both the business and historical context of the IC design and manufacturing process. (Mentor Graphics)

CHALK TALK Accelerate SoC and ASIC Verification Using FPGA Prototypes. Join Amelia Dalton as she explores methods of ASIC verification available today and why FPGA-based prototypes offer the most affordable and most powerful solution. (Synplicity)

CHALK TALK Advancing SoC Verification Methods.
Join Amelia Dalton as she talks with experts from Mentor Graphics on processor-driven test and other techniques for solving your system-on-chip verification problems. (Mentor Graphics)

CHALK TALK Did you miss the ARM Developers' Conference? Join Amelia Dalton for Journal Webcasts' coverage of the event - it'll be just like you were there! (Journal Webcasts)

Methods for Reducing Marketing Jitter Through Filtering of Marketing Noise in Conference Presentations
(Bryon Moyer)

Related Applications
None.

Field of the Invention
Way out in left field.

Background of the Invention
For purposes of gathering together for reasons including but not limited to sharing information, making commercial announcements, receiving training, professional networking, escaping a nagging spouse or children, and racking up frequent flier miles, it is common for engineering professionals to attend conferences or conventions. Such conferences may consist of convention-center catered meals, speeches in which very important people say what everyone already knows, an exhibit hall wherein more women are employed than in the remaining entirety of the technology industry, and various panels and presentations intended to provide information from presenter to audience.

For most such conferences, the tone of the panels and presentations may be expected to be professional and technical, with minimal intrusion by commercial considerations. In the course of assembling such panels and inviting speakers to prepare presentations, it may occur that the technical information being communicated experiences high levels of marketing noise injection. This creates reluctance by engineers to attend such highly noisy presentations, a phenomenon referred to as marketing jitter. [more]

Attacking Abuses of Power - Part 2
(Bryon Moyer)

A few weeks ago, we started looking at ways of reducing power consumption when designing SoCs. We divided the world into the front-end, where the big payoff is, and the back-end, with useful techniques that have less dramatic impact. We looked at architecture and system design, hardware/software allocation and C-to-RTL, multicore, Multi-Voltage Supply (MVS), power switching, Dynamic Voltage/Frequency Scaling (DVFS), and Adaptive Voltage Scaling (AVS). These are techniques that can give power savings in the range of 30-50%. Having addressed those, there are numerous back-end techniques that can give more modest, but nonetheless valuable, power savings. We’ll look at some of those here, not necessarily in any specific order. The savings from these techniques will vary widely by application but will generally be in the 5-
15% range.

One technique that has been used for quite a while is to provide different transistors with different thresholds in the design kit -- so-called multi-VT design. Low-threshold transistors are faster but also leak more. Not all transistors need to be the same speed – in fact, a majority of the transistors are not likely to be in the critical path, so higher-VT transistors can be used. While in the past extra speed meant extra breathing room, today extra speed means wasted power. So if a path is faster than it needs to be, it can be slowed down by swapping out transistors (among other things).

Similar to using different transistors, some tools will allow the use of faster or slower flip-flops, according to the needs of the critical path. While the different flip-flops might make use of transistors with different thresholds, this also allows other techniques to be used in combination to provide faster or lower-power flip-flops. [more]