a techfocus media publication :: March 11, 2008 :: volume I, no. 10

FROM THE EDITOR

This week, we have a double feature.  Bryon Moyer brings us a look at the magic behind merging digital and analog design techniques in today’s 45nm technology with Magma’s Titan environment.  In many companies, digital and analog engineers live in separate buildings and almost never attend the same barbecues, so how do we keep their work all playing nicely on one chip?  Bryon’s latest feature has the details.

Next, Dick Selwood, our European Editor makes his IC Journal debut with a look at Accelera.  Standards bodies tend to run the gamut from industry-critical workhorses to blatant boondoggles.  Accelera leans toward the workhorse end of the scale.  Dick Selwood reveals the secrets in his latest feature.

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Kevin Morris – Editor in Chief
Techfocus Media, Inc.

EVENTS & ANNOUNCEMENTS

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FPGA-based prototyping is evolving from an ad-hoc tool
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LATEST NEWS

March 11, 2008

Real Intent's Bug Hunting Software Takes Center Stage at DATE in Munich

Electronics Industry Embraces Synplicity’s Confirma Platform for ASIC Verification

Skyworks Solutions Selects Berkeley Design Automation Analog FastSPICE™ for Multi-mode 3G Transceiver Simulation

Carbon Design Systems to Showcase Carbon Model Studio This Week at DATE

March 10, 2008

New IP-XACT Specification to Aid Design and Advanced Verification

Gerhard Angst, Founder and CEO of Concept Engineering, Receives EDA Achievement Award

The MathWorks to Share Expertise on Multidomain Modeling and System-Level Verification at Date 2008

ProDesign Launches the CHIPit Iridium Prototyping Suite

Solido Design to Present Seminar at DATE Exploring Variation Robustness for Analog, Custom Digital and Memory Desig

Synopsys HSPICE Delivers Innovative Technology to Accelerate Circuit Simulation Performance

IR’s IR3502 XPhase® Control IC Provides Highly Flexible Intel® VR11.0 and VR11.1 Processor-Based Power Solutions

Open SystemC Initiative Adds Texas Instruments, Maple Design, Virtutech to Member Roster

Synopsys Announces Multi-Core Initiative to Accelerate Design Time-To-Results

March 7, 2008

Sequence CTO Frenkil Details Ultra-Low Leakage Power Strategy at DATE

March 6, 2008

ISQED 2008 Panelists to Debate Quality in Design, ESL, and Manufacturing Trends

Micrologic Announces the Production Release of Its nanoRVInteractive™

March 5, 2008

EVE Unveils ZeBu-Personal at DATE

The MathWorks Introduces New Versions of MATLAB and Simulink Product Families

Certess Announces Broad Adoption of Its Functional Qualification Solution by STMicroelectronics

Solido Design to Present Seminar at DATE Exploring Variation Robustness for Analog, Custom Digital and Memory Design

Ricoh Integrates Carbon Design Systems into ESL Design Flow

CURRENT FEATURE ARTICLES

A Merger of Unequals
Magma Announces the Union of Analog and Digital in Titan
(Bryon Moyer)
Do Converging Standards Meet at Infinity?
(Dick Selwood)
Power Plays: Raising the Stakes
Synopsys Announces Eclypse for Low Power

(Bryon Moyer)
The Very Model Of Reusability
(Bryon Moyer)
Attacking Abuses of Power – Part 1
(Bryon Moyer)
The Green Monster Stirs
(Bryon Moyer)
DesignCon Steps it Up
Eye Candy for the Digital Designer (Kevin Morris)

JOURNAL WEBCASTS

NEW!! CHALK TALK Crossing the Gap between Algorithm and Hardware Implementation. Join Amelia Dalton as she learns how C++ and Catapult C Synthesis can accelerate the design, implementation, and verification of complex system-level algorithms. (Mentor Graphics)

Approaching Yield in the Nanometer Age. This tutorial goes into detail on DFM technical challenges and solutions within both the business and historical context of the IC design and manufacturing process. It shows the importance of the fabless model as part of a more holistic DFM methodology, and includes demonstrations of what the new tools look like. (Mentor Graphics)

CHALK TALK Accelerate SoC and ASIC Verification Using FPGA Prototypes. Join Amelia Dalton as she explores methods of ASIC verification available today and why FPGA-based prototypes offer the most affordable and most powerful solution. (Synplicity)

CHALK TALK Advancing SoC Verification Methods.
Join Amelia Dalton as she talks with experts from Mentor Graphics on processor-driven test and other techniques for solving your system-on-chip verification problems. (Mentor Graphics)


CHALK TALK Did you miss the ARM Developers' Conference? Join Amelia Dalton for Journal Webcasts' coverage of the event - it'll be just like you were there! (Journal Webcasts)


A Merger of Unequals
Magma Announces the Union of Analog and Digital in Titan (Bryon Moyer)

As the orks circled the tower in growing numbers, efforts to finish the weapon became increasingly frantic. The mechanical portion was almost complete: all of the strength and stress tests had passed, so the structure was ready to go. They had done practice shots with weights equivalent to the final payload, and distance and accuracy looked good. They fiddled a bit more with the pivots and joints to make sure that wear wouldn’t be excessive. But the real thing they were waiting for was the payload itself. This was a mystery concoction brewed up by some tall mysterious guy with a long beard and a pointy hat in one of the secure rooms near the top of the tower. They had no idea what it was or how he made it. They knew only that it would be poured into the carrier through some system of tubes. They had tested the tubes with water, but because they didn’t know the chemistry of the actual payload, they couldn’t be sure that viscosity wouldn’t be an issue, or even that the liquid wouldn’t react with the tubing or the carrier. And once the payload was ready, they had no time to run a whole new set of tests; the advancing hordes weren’t of the genteel sort that would put their attack on hold while T’s were being crossed. No, they simply had to assume that mystery dude knew how to brew the goo, put it in the shell, and hope it worked. [more]


Do Converging Standards Meet at Infinity?
(Dick Selwood)

The problem with standards is that they frequently take a long time to determine. Going from “Wouldn’t it be a good idea to have a standard way of doing this?” to actually having a document agreed upon and published can take many years, and frequently the world has moved on. And companies enter the standards process for different reasons: it has even been suggested that some companies join groups preparing standards just so that they can scupper them.  But that would be too cynical a thought, wouldn’t it?

Accellera’s chair, Shrenik Mehta, of Sun, has no truck with the traditional standards process. His view is that it is important to get a standard accepted and in use as soon as possible, particularly in the EDA field. Accellera’s name reflects this, and its method of working is designed to achieve it. [more]


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