CURRENT FEATURE ARTICLES

Power Plays: Raising the Stakes
Synopsys Announces Eclypse for Low Power
(Bryon Moyer)
The Very Model Of Reusability
(Bryon Moyer)
Attacking Abuses of Power – Part 1
(Bryon Moyer)
The Green Monster Stirs
(Bryon Moyer)
DesignCon Steps it Up
Eye Candy for the Digital Designer (Kevin Morris)
A Bid to Simplify Flash Subsystem Design
(Bryon Moyer)
45nm From 30,000 ft
(Bryon Moyer)
Burning the Secret Sauce
When Paranoia Impedes Progress (Kevin Morris)

JOURNAL WEBCASTS

NEW!! Approaching Yield in the Nanometer Age. This tutorial goes into detail on DFM technical challenges and solutions within both the business and historical context of the IC design and manufacturing process. It shows the importance of the fabless model as part of a more holistic DFM methodology, and includes demonstrations of what the new tools look like. (Mentor Graphics)

CHALK TALK Accelerate SoC and ASIC Verification Using FPGA Prototypes. Join Amelia Dalton as she explores methods of ASIC verification available today and why FPGA-based prototypes offer the most affordable and most powerful solution. (Synplicity)

CHALK TALK Advancing SoC Verification Methods.
Join Amelia Dalton as she talks with experts from Mentor Graphics on processor-driven test and other techniques for solving your system-on-chip verification problems. (Mentor Graphics)

CHALK TALK Did you miss the ARM Developers' Conference? Join Amelia Dalton for Journal Webcasts' coverage of the event - it'll be just like you were there! (Journal Webcasts)

The cards having been dealt, he took a peek at his down cards. A king… not bad… a 2… now why couldn’t we be playing “low-card-in-the-hole?” At least he wasn’t playing Texas Hold-em, the only game people seemed interested in anymore, and for reasons that were completely beyond him. There were so many other interesting varieties; hell, these days, even a plain old game of seven-card stud seemed downright novel. Jack showing; time to bet… let’s see that next card.

While not suggesting a random or luck component in EDA products, with broad areas like low power design, building an offering can be much like building a good poker hand: you lay on the features as you can until you’ve got what you hope will be the best hand. And an occasional show of bravado doesn’t hurt either.

So interleaved with our series on low-power design techniques is an announcement by Synopsys of their new Eclypse offering with a focus on low-power design. We’ve covered some of the issues before, and some we have yet to discuss, so we’ll do a bit of review for the former and a bit of preview for the latter.

As testament to the currency of low-power design, even though Synopsys has been adding low-power features over the last few years, they are actually branding their low-power solution as of this release under the Eclypse moniker. Part of this may be a “the time is right” thing, but part of it could reasonably be their completed support for a simple unifying element: the Unified Power Format, or UPF file. This is the latest standardized file format that allows you to specify your intentions with respect to power. Power domains, levels, gating, behaviors, and much more can be captured in one place and then be used throughout the entire toolchain. A single specification can drive synthesis and then be used as a benchmark for validation. So even if Synopsys had added no new capabilities, simply adding UPF support would have served to unify their offering from a power standpoint. [more]