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45nm From 30,000 ft
by Bryon Moyer, IC Design and Verification Journal
Building a house used to be so easy. You found some flat land. You chopped down some trees. You sawed them up and put them together. Voilà! Honey, I’m home! And if a big storm knocked it down, you built another one, perhaps a bit stronger.
OK, maybe that’s not easy; it actually sounds like a lot of work, but it was conceptually simple. Today just try building a house. You’ve got permit after permit. Are the electricals up to snuff? Did the wallboard get nailed up properly? Where does the runoff from the gutters go? Wanna add a few windows to that windowless wall? OK, does that screw up the shear strength of the wall in case there’s an earthquake? How does the extra glass affect the energy rating of the house? Nobody ever cared about this stuff before; now it’s routine.
This didn’t happen overnight. It was a gradual process of trial and error, and as mistakes were made and needs changed, guidelines were added, and guidelines became rules, and more guidelines were added and they eventually became rules. And all of the rules are presumably there for some good reason (that may or may not be readily apparent). And this made building a house more expensive, so that the economics meant fewer house designs, and more houses from each design - as evidenced by row upon row of identical houses in modern tracts.
This should sound familiar to any IC designer that has watched process nodes migrate from micron-level through sub-micron, sub-half-micron, and now the nanometer realm. And the changes have been coming thick and fast since the 100nm barrier was crossed. Every couple nodes brings a major change of some sort, a big issue that grabs everyone’s attention. At 180nm, timing closure was the big issue; at 130 nm, it was all about signal integrity. At 90nm, power ruled. In each case, items that used to be 2nd- or 3rd-order considerations gradually moved up until they finally achieved 1st-order status.
Today 90nm is in full volume production; 65nm is the mainstream design node, and 45nm is now the leading-edge node on which a few companies are seeing silicon. At 65nm, manufacturing became a real design consideration; at 45nm, it’s all about manufacturing. Design For Manufacturing, or more typically, DFM (or Design For Yield – DFY), is all over the product literature and websites of EDA vendors. [more]
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