ProDesign Opens New Era of ASIC Prototyping with CHIPit Manager Pro

Software Handles Design Implementation Flow from RTL, Reduces Compilation Time Through Parallel Synthesis Process

SANTA CLARA, Calif.--(BUSINESS WIRE)--ProDesign, leading supplier of high-speed ASIC and SoC verification platforms, today launched CHIPit Manager Pro, a new register transfer level (RTL) front-end software that takes RTL directly into the CHIPit ASIC Prototyping systems.

The new software includes a complete design implementation flow, including RTL parsing, dependency check, synthesis, partitioning, clock tree, bus and memory handling. The easy-to-use CHIPit Manager Pro software guides the user step-by-step through the design implementation flow. A full dependency check makes sure all important steps or settings have been done.

The new software is optimized for CHIPit hardware and takes full advantage of the system’s flexible interconnection architecture. The tool routinely analyzes the design (clock/reset nets, black boxes, size, etc.) before it runs the partitioning. The design partitioning can be done by the net-list compiler manually, automatically or a combination of both. The net-list compiler automatically finds the right number of interconnections between the different FPGAs and extension boards and the best placement of FPGAs and extension boards.

"Third party tools did not provide the smooth working solution or utilize the performance and capabilities of our CHIPit products. Our CHIPit Manager Pro software puts ASIC Prototyping into a new era of hardware assisted verification," stated Heiko Mauersberger, CTO of ProDesign.

With its new incremental design implementation flow the CHIPit Manager Pro only changes targeted modules and files and leaves other parts untouched. This approach reduces the time for repetitive design implementation dramatically and gives the user much more time to work on the actual design verification.

The CHIPit Manager Pro synthesis process is handled in parallel on block level and all individual tasks that allow it will be done by load sharing tools such as LSF or Open Batch. This reduces the design implementation flow to a minimum, and makes ASIC Prototyping much more attractive.

For more information please visit: http://www.uchipit.com.

©2008 Business Wire. All of the news releases contained herein are protected by copyright and other applicable laws, treaties and conventions. Information contained in the releases is furnished by Business Wire's members, who warrant that they are solely responsible for the content, accuracy and originality of the information contained therein. All reproduction, other than for an individual user's personal reference, is prohibited without prior written permission.