Calypto to Present RTL Power Optimization Solution at EDSFair 2008

Also Featured Will be Calypto’s Recently Announced SLEC System-HLS
EDSFair
Booth No. 301

SANTA CLARA, Calif.--(BUSINESS WIRE)--Calypto™ Design Systems Inc., the leader in sequential analysis technology, will demonstrate PowerPro™ CG and SLEC™ System-HLS in Booth #301 during the Electronic Design & Solution Fair (EDSFair) 2008 January 24-25 at the Pacifico Yokohama in Yokohama, Japan.

Additionally, Calypto will offer daily seminars on reducing power titled, “Automating Power Optimization for RTL designs,” January 24 from 11:30 a.m.-12:15 p.m. in Room DM3-24-2 and January 25 from 10:30-11:15 a.m. in Room DM6-25-1.

PowerPro CG (for Clock Gating), Calypto’s automated register transfer level (RTL) power optimization solution, dramatically reduces power consumption by applying sequential analysis at the RTL to identify micro-architectural optimizations that result in a lower power circuit. Demonstrations at the Calypto Booth throughout EDSFair will highlight PowerPro CG’s ability to analyze RTL across multiple clock cycles to identify sequential clock-gating opportunities.

Also being shown will be Calypto’s recently released SLEC (Sequential Logic Equivalence Checker) System-HLS that comprehensively verifies high-level synthesis (HLS) output. SLEC System-HLS tightly integrates SLEC System into HLS design flows by automating setup and supporting HLS language extensions, such as Algorithmic C™ datatypes from Mentor Graphics® and System C Modular Interfaces from Forte Design Systems.

For more details on Calypto, visit: http://www.calypto.com.

For more information on EDSFair 2008, visit: www.edsfair.com.

About Calypto

Founded in 2002, Calypto Design Systems, Inc. enables SoC design teams to bridge System and RTL for semiconductor design, saving millions of dollars in design costs and silicon re-spins. Enabling ESL, Calypto delivers software products to leading-edge semiconductor and systems companies worldwide. Calypto is a member of the Cadence Connections program, the IEEE-SA, Synopsys SystemVerilog Catalyst Program and the Mentor Graphics OpenDoor program. Corporate Headquarters is located at: 2933 Bunker Hill Lane, Suite 202, Santa Clara, Calif. 95054. Telephone: (408) 850-2300. More information about Calypto may be found at: http://www.calypto.com

Mentor Graphics is a registered trademark of Mentor Graphics Corporation. Catapult C and Algorithmic C are trademarks of Mentor Graphics. Cynthesizer is a trademark of Forte Design Systems. Calypto, PowerPro, SLEC and Enabling ESL are trademarks of Calypto Design Systems Inc. Other products and company names may be trademarks or registered trademarks of their respective companies.

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