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| Source: Real Intent Real Intent Demonstrates Formal Verification Software for Bug Hunting, Verifying Clock Domain Crossing Signals, Assertions and Timing Constraints at EDSFair2008EnVision Family Improves Designer Productivity for SoC Design Verification Who/What: The demonstrations feature Real Intent's EnVision™ Family of software. These include: Ascent™, an automatic bug hunting tool that can run even before simulation on Register Transfer Level (RTL) designs, requires no testbench, and supports both the Property Specification Language (PSL) and SystemVerilog Assertions (SVA) constraints; Conquest™, an Assertion-Based Verification (ABV) tool with engines that excels in capacity and performance when compared to competing products; Meridian CDC, a checker for the integrity of signals crossing clock domains; which includes the most comprehensive 3 strategies in industry, including Structural, Dynamic, and Formal. and PureTime™, automatic software for verifying timing exception constraints such as Synopsys Design Constraints for set_false_path and set_multicycle_path commands. When/Where: Information About Real Intent Real Intent is headquartered at 505 North Mathilda Avenue, Suite 210, Sunnyvale, CA 94085, phone: (408) 830-0700 fax: (408) 737-1962, web: www.realintent.com, e-mail: info@realintent.com.
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