Source: Calypto
January 17, 2008

Calypto Adds SLEC System-HLS to Product Line, Enabling ESL, Capturing Growing Market

Integration with High-Level Synthesis Tools Extends SLEC’s Proven Capabilities

SANTA CLARA, Calif. –– January 14, 2008 –– Calypto™ Design Systems, the leader in sequential analysis technology, announced today immediate availability of SLEC™ System-HLS for comprehensive verification of high-level synthesis (HLS) output.

Enabling ESL™, SLEC (for Sequential Logic Equivalence Checker) is the semiconductor industry’s only functional verification solution to formally verify equivalence between electronic system level (ESL) models and register transfer level (RTL) implementations.

“ASIC design teams require an ESL flow that creates high-quality, functionally correct RTL from system-level models,” describes Simon Bloch, general manager of Mentor Graphics Design and Synthesis Division. “Mentor’s Catapult® C Synthesis is used today by the top semiconductor houses to design some of their most complex ASIC hardware. The certified integration between Catapult C and SLEC offers these same designers a complete ESL synthesis and verification flow from ANSI C++ algorithms to functionally equivalent RTL output.”

SLEC System-HLS tightly integrates SLEC System into HLS design flows by automating setup and supporting HLS language extensions, such as Algorithmic C™ datatypes from Mentor Graphics® and System C Modular Interfaces from Forte Design Systems. SLEC System-HLS comprehensively verifies the RTL code synthesized from system-level models without the need for writing testbenches or running simulation. SLEC System-HLS is included in the recent SLEC 3.0 software release that also increases capacity and optimizes formal algorithms for system-level design styles.

“We continue to see a dramatic increase in the number of companies using HLS on production designs,” says Tom Sandoval, Calypto’s chief executive officer. “SLEC 3.0 is the result of our significant investment in system-level solutions, allowing us to serve a larger portion of the growing ESL market.”

Additionally, SLEC 3.0 extends ESL language support beyond the established synthesizable subset. SLEC’s expanded C/C++ and SystemC language processing capabilities support a wider array of coding constructs, including dynamic memory and arbitrary pointers.

Pricing and Availability
SLEC System-HLS is an added option to SLEC System and currently supports Mentor Graphics’ Catapult C and Forte Design Systems’ Cynthesizer™ HLS flows. Each HLS solution is sold separately and is priced at $50,000 for a one-year, time-based license.

The SLEC product family also includes: SLEC System for verifying manually created or synthesized RTL with C/C++/System C models; SLEC RTL for verifying sequential RTL optimizations for power and performance; and SLEC CG (clock gating) for verifying the output of PowerPro™ CG. PowerPro CG, announced by Calypto last year, is an automated power optimization solution for RTL designers.

About Calypto
Founded in 2002, Calypto Design Systems, Inc. enables SoC design teams to bridge System and RTL for semiconductor design, saving millions of dollars in design costs and silicon re-spins. Enabling ESL, Calypto delivers software products to leading-edge semiconductor and systems companies worldwide. The company is privately held with venture funding from Cipio Partners, JAFCO Ventures, Tallwood Venture Capital and Walden International. Calypto is a member of the Cadence Connections program, the IEEE-SA, Synopsys SystemVerilog Catalyst Program and the Mentor Graphics OpenDoor program. Corporate Headquarters is located at: 2933 Bunker Hill Lane, Suite 202, Santa Clara, Calif. 95054. Telephone: (408) 850-2300. More information about Calypto may be found at: http://www.calypto.com