FPGA and Structured ASIC JournalIC Design and Verification Journal
HOME :: JOB LISTINGS :: WEBCASTS :: ARCHIVES :: MEDIA KIT :: SUBSCRIBE :: FORUMS
   

May 14, 2008

DesignAdvance Releases CircuitSpace® v2.2 Unveils New Cross-Probing Technology

Kilopass Invites DAC Attendees to Learn about High Value SOC Design Requirements for One Time Programmable Memory

Synplicity Announces Shareholder Approval of Agreement of Merger With Synopsys, Inc.

Renesas Adopts Cadence SoC Encounter for Large Scale Complex Chips and Flip-Chip Design

Kilopass Invites SoC Designers to Attend 2nd Annual Embedded Non-Volatile Memory Symposium

May 13, 2008

HiSilicon Selects Synopsys as IP Vendor Of Choice for SoC Designs

Berkeley Design Automation Delivers Over 2x Superior Price/Performance Versus All True SPICE Accurate Circuit Simulators

Mentor Graphics Offers Personalized Web Support Portals; First to Earn Certification under the SCP eService Standard

45th Design Automation Conference Panels Cover Industry’s Varied Interests, Challenges, Direction, Future

Synopsys HSIM-XA Adopted by STMicroelectronics for Its Advanced Smart Power Technology

IC Design & Verification Online Events -- On-Demand
View presentations, product demos and
tutorials -- all from your desktop.
It's easy, free and convenient!
Click Here!

May 12, 2008

High-performance MIPS32(R) 24K(R) Processor Core Powers New GPON Residential Gateway SoC From BroadLight

Synopsys Donates Proven VMM Methodology Library and Applications to Accellera

The MathWorks Simplifies Development Of Parallel Applications in MATLAB

CoWare and Agility Team to Accelerate the Simulation of Complex DSP Algorithms

Enhanced Carbon Model Studio Reduces Time to Create Models

May 8, 2008

NextIO Standardizes on VMM Methodology and Synopsys VCS for Next-Generation I/O Virtualization Chip

Coverity™ Introduces Thread Analyzer for Java

May 7, 2008

Accellera Continues Support for Verification and Interoperability with Formation of New Standards Committee

Agilent Technologies Introduces Industry-First Flying Leads Probe for Embedded PCI Express® 2.0 Design, Validation

Mentor Graphics Aligns Product Groups to Address IC Implementation Challenges at 45nm and Beyond

Cypress Unveils Online Solutions Library To Facilitate Faster, More Efficient PSoC® Designs

Agilent Technologies' Infiniium 90000A Series 13-GHz Oscilloscope Approved by PCI-SIG(r) for PCI Express® 2.0 Compliance Testing

Mixed-Signal ASICs from ChipX
- USB 2.0 & PCI Express ASIC Designs and FPGA conversion
- USB-IF & PCI-SIG certified ASICs
- Standard Cell, Hybrid ASIC and Structured ASIC solutions
- Low NRE, fast Time to Market, USB & PCIe ASIC platforms
Click Here to Win a PCIe Development Board

May 6, 2008

Tektronix Introduces Most Comprehensive Test Set for Next Generation DDR3 Memory

Synopsys Invests In Prover Technology

Mentor Graphics Announces Partnership with NXP Semiconductors for Design-for-Test Tools and Technology

National Instruments to Host NIWeek 2008 Graphical System Design Conference

Jazz Semiconductor Announces Call for Papers for 2008 Analog-Intensive Mixed-Signal Circuits, Applications, and Technology (AIMS-CAT) Conference

[previous news]

Free Job Postings on Journaljobs.com
JournalJobs.com – the job board for FPGA Journal, Embedded Technology Journal, and IC Journal is now re-launching with a host of new features and capabilities. In celebration of JournalJobs.com grand re-opening, we’re offering free job postings through July 31, 2008. Go online, post a job, pay nothing, and watch for those qualified resumes to come knocking on your inbox.
Click here to post your job listing on journaljobs.com


Google
 

Three Chords and the Truth
Aart de Geus and Synopsys go Quick to Four
(Kevin Morris)


Avoiding Failure Analysis Paralysis
Cadence Describes the DFM-Diagnostics Link
(Bryon Moyer)


Almost Instant Replay
Mentor Announces Codelink for Debugging Processor-Driven Tests
(Bryon Moyer)


The Spirit of Standardization
IP Re-use Takes Center Stage (Kevin Morris)

Accommodating Change
Cadence Announces a Front-End ECO Tool (Bryon Moyer)


Making Quality Everyone’s Business
A Quick Look at isQED
(Bryon Moyer)

Methods for Reducing Marketing Jitter Through Filtering
of Marketing Noise in Conference Presentations (Bryon Moyer)

Attacking Abuses of Power - Part 2
(Bryon Moyer)


ISSCC Processor Fest
(Bryon Moyer)

Bigger and Better Storage
(Bryon Moyer)

[previous feature articles]

NEW!! CHALK TALK Low Power Design With Xilinx and Linear Technology. Join Amelia Dalton as she chats with Mark Moran of Xilinx and Afshin Odabaee of Linear Technology about low power FPGA based designs.(Xilinx)

CHALK TALK Designing Embedded Systems With Linux and low cost FPGAs Join Amelia Dalton as she chats with industry experts about simplifying embedded systems design with Linux running on low-cost programmable system-on-chip platforms.(Xilinx)

CHALK TALK Lowest Total System Cost With Xilinx Spartan-3 Amelia Dalton chats with Mark Moran of Xilinx about reducing your overall system cost with the Xilinx Spartan-3 family of FPGAs. (Xilinx)

CHALK TALK Low Cost FPGA with Serdes Lattice ECP2M Amelia Dalton talks with Bertrand Leigh of Lattice Semiconductor about low-cost FPGAs with multi-gigabit SerDes interface capability. (Lattice Semiconductor)

CHALK TALK Crossing the Gap between Algorithm and Hardware Implementation. Join Amelia Dalton as she learns how C++ and Catapult C Synthesis can accelerate the design, implementation, and verification of complex system-level algorithms. (Mentor Graphics)

Approaching Yield in the Nanometer Age. This tutorial goes into detail on DFM technical challenges and solutions within both the business and historical context of the IC design and manufacturing process. It shows the importance of the fabless model as part of a more holistic DFM methodology, and includes demonstrations of what the new tools look like. (Mentor Graphics)

[previous webcasts]

May 13, 2008 - This week, we did a round of improvisational interviewing with Aart de Geus – Synopsys co-founder, blues musician, and general Renaissance man.  Our latest feature gets his thoughts on the EDA industry, Gibson guitars, Moore’s Law, and “techonomics”.  

Thanks for reading! If there's anything we can do to make our publications more useful to you, please let us know at:
comments@ICJournal.com. If you'd rather sound off in public, please post your comments or questions in our new Journal Forums.

Kevin Morris – Editor in Chief
Techfocus Media, Inc.



Three Chords and the Truth
Aart de Geus and Synopsys go Quick to Four (Kevin Morris)

Twelve Bar Blues is structured improvisation.  A standard twelve-measure chord progression repeats tirelessly, and the experienced blues musician lays his soul over this monotonous harmonic structure like a fine linen drapery.  Aart de Geus, President, CEO, and Co-Founder of Synopsys, the world’s second largest electronic design automation (EDA) company, is also an accomplished blues guitarist. 

Blues in C
I (C) Measures 1-4:

The tonic orients the ear, providing a firm foundation of reference.  In traditional blues, it is repeated for the first four bars of the sequence, setting up “home base” for the listener’s mind.  When Aart de Geus co-founded Synopsys over two decades ago, logic synthesis was the tonic - the root chord upon which the engineering-centric company was founded.  Logic synthesis set the key values of creativity, learning, and technological innovation that hardened the fledgling company so that it could survive and thrive in the tempestuous torments of two decades of The Moore’s Law blues.

“I played guitar starting around 14 years old,” begins de Geus.  “It was very much around the campfire, scouts, gospel, Bob Dylan – those types of things.  Then, somewhat by accident, I went to a couple of great blues concerts in Switzerland, where I grew up.  It just hit me – a guy by the name of T-bone Walker, who was considered one of the fathers of Blues, was performing there.  It was a big concert, not a small venue like a bar or anything, and after that I really never played anything else.”
[more]



Avoiding Failure Analysis Paralysis
Cadence Describes the DFM-Diagnostics Link (Bryon Moyer)

Back when I was a product engineer working on bipolar PALs (oops – I mean, PAL® devices), one of my main activities was figuring out what was wrong. That was most of the job of a product engineer: fix what’s broken. You don’t spend any time working on the stuff that’s working, you work on what isn’t working. Assuming it’s a chip that’s wrong, the process would typically start with a trip into the testing area to put a part on the tester and datalog it to see some evidence of things going awry. Armed with that, the next job was to spread a big schematic out on a table and start looking at the circuits, figuring out what could be causing the problem. You’d come up with a couple scenarios, and next you’d have to look in the actual chip.

Of course, in order to look at the chip, we had to spread a big layout sheet on a table to trace out where the circuits were physically located. Then we’d know where to look. The chip would have to be decapped – I could do that myself if it was a CERDIP (ceramic packaging, where you could pop off the top); otherwise you needed to go to one of those scary guys that knew just a bit too much about chemistry (and whom you wanted to keep happy with occasional gifts of jerky or sunflower seeds) to have a hole etched in the plastic. Hopefully that was enough, and then you could go into the lab and use microscopes and microprobes and oscilloscopes and such to poke through dielectric layers, perhaps cut a metal line to get to something below, and with any luck you’d identify a problem that could be fixed. In the worst case you had to go back to Scary Guy for more delayering, or perhaps a SEM session. Or – yikes – chemical analysis. It was all seat-of-the-pants, using forensic techniques worthy of CSI – Jurassic Edition, and you let your data and observations tell you what the next step should be. [more]



Almost Instant Replay
Mentor Announces Codelink for Debugging Processor-Driven Tests
(Bryon Moyer)

It’s 4th and goal, 0:15 to go in the last quarter. The ball is snapped, the quarterback steps back, finds his receiver, and throws. Seeing the play develop, the defender runs to cover the receiver. They both jump in an aerial pas de deux; the ball dances elusively into the air, spins tantalizingly near outstretched fingertips, and falls harmlessly to the ground. While the defender gyrates around in a rather improbable new display of exultation that he hopes will sweep the nation, the receiver cries interference and looks to the referees for justice. The referees call upstairs for a replay so they can judge what happened. To their amazement, they’re told, “Um… we weren’t filming. We can’t see what happened.”

“So, what are we supposed to do?? How are we going to resolve this?”

“Well, I know this is going to sound strange, but the teams are going to have to completely replay the second half, exactly as it happened the first time, so that we can watch that pass more closely.” [more]



The Spirit of Standardization
IP Re-use Takes Center Stage (Kevin Morris)

Edgar was seldom in the office – even before the current trends in telecommuting and working from home exploded.  He’d waltz through the cube aisles looking important at least once or twice per week – tossing a gigantic notebook with DRAFT stamped on the top onto the desk of some unsuspecting victim.  The target would immediately activate his defenses – talking about how he was behind on his part of the project and was almost critical path right now.  Edgar wasn’t fazed.  Sure, reviewing this draft of the spec might impact this one project at this one company – but Edgar was in this for the Greater Good.  Edgar was a big picture guy – no, more than that.  Edgar was a chronic career committee member.

Every engineering organization has at least one Edgar – the engineer that volunteers for every consortium and “working group” that comes along.  Most of these efforts will go nowhere – and that’s just the way Edgar likes it.  Specifications will be reviewed and modified in perpetuity. Power struggles will ensue amongst idealistically opposing factions debating semantics of corner cases that no real-world scenario will ever see, and corporate one-upsmen will work to be sure that nothing happens that will compromise competitive advantage or benefit a rival. 
[more]



Accommodating Change
Cadence Announces a Front-End ECO Tool (Bryon Moyer)

Someday someone will invent a useful engineering feature that can be plugged into telephone and email systems. Once an engineering project gets within a certain range of being complete, it will completely disconnect marketing so that they will have no way of radioing in feature changes at the last minute. But until that time, you know it’s gonna happen. And then you’re going to have to fight the fight over whether the change is worth it. [more]



Making Quality Everyone’s Business
A Quick Look at isQED (Bryon Moyer)

Nestled amongst the big noisy conventions like CES, ISSCC, and DAC can be found some more modest, highly focused conferences. These shows may cast a smaller shadow, but they may also benefit from the lack of attendant hoopla, since marketing pays less attention and engineers can focus on the business at hand. One such show that just took place was isQED, or the International Symposium on Quality Electronics Design. Now in its ninth year, isQED focuses on the interactions between design, test, quality, and manufacturing disciplines in the effort to improve such aspects as yield, quality, and robustness. [more]



Methods for Reducing Marketing Jitter Through Filtering of Marketing Noise in Conference Presentations
(Bryon Moyer)

Related Applications
None.

Field of the Invention
Way out in left field.

Background of the Invention
For purposes of gathering together for reasons including but not limited to sharing information, making commercial announcements, receiving training, professional networking, escaping a nagging spouse or children, and racking up frequent flier miles, it is common for engineering professionals to attend conferences or conventions.
[more]



Attacking Abuses of Power - Part 2
(Bryon Moyer)


A few weeks ago, we started looking at ways of reducing power consumption when designing SoCs. We divided the world into the front-end, where the big payoff is, and the back-end, with useful techniques that have less dramatic impact. We looked at architecture and system design, hardware/software allocation and C-to-RTL, multicore, Multi-Voltage Supply (MVS), power switching, Dynamic Voltage/Frequency Scaling (DVFS), and Adaptive Voltage Scaling (AVS). These are techniques that can give power savings in the range of 30-50%. Having addressed those, there are numerous back-end techniques that can give more modest, but nonetheless valuable, power savings. We’ll look at some of those here, not necessarily in any specific order. The savings from these techniques will vary widely by application but will generally be in the 5-15% range.
[more]



ISSCC Processor Fest
(Bryon Moyer)

There are some places it seems everyone wants to be. The Oscars. An inaugural ball. Mardi Gras. New Years in Times Square. (OK, pre-War on Terror.) Well there was a new member of this list last week that might not have sprung to mind immediately: the microprocessor session at ISSCC, packed to the gills. Four new processors were presented, plus one process migration to 45 nm. The bragging rights on such chips are typically all about performance (or performance efficiency), and everyone fusses over clock rates and bus sizes and various and sundry other numbers, but, in this article, we’ll focus away from the distracting lure of feeds and speeds. Anyone can look up the numbers in a datasheet, and the techno-paparazzi have assuredly posted pictures of the most lurid ones already. So we’ll focus on things that we found interesting in the new processors, assuming that what interests us will interest you.
[more]



Bigger and Better Storage
(Bryon Moyer)

I don’t know what it is about people, but we seem to excel at accumulating more and more stuff and needing more and more space to put it. And it used to be that we only did it in the real world, amassing real things and then ensconcing them in public storage units until time to move to a new house – which means moving the stuff to a new public storage unit. But now we’re doing it in the virtual world as well, and we keep needing more room to put stuff. One place we store stuff is solid-state non-volatile memory. Yeah, we still use hard disks. But if solid state technology keeps on at the current rate, we can soon reach the much-desired goal of a solid state hard drive.
[more]


[archives]

 
All material on this site copyright © 2008 techfocus media, inc. All rights reserved.
IC Design and Verification Journal
Privacy Statement