The availability of devices incorporating hardened ARM® applications processors closely coupled to an on-chip FPGA fabric opens a world of possibilities to electronic system designers. However, these devices also introduce novel design, debug, and optimization challenges. New development methodologies are required to address software and hardware integration issues and system-level performance optimizations efficiently at a price affordable by small- and medium-sized companies. This white paper outlines Altera and ARM’s latest innovations in on-chip debug logic, FPGAs, and software debug and analysis tools aimed to address these challenges.
In the past, FPGA vendors commonly segmented their portfolios between "high-end" and "low-cost" devices. However, as developers have refined the way they leverage FPGA technologies, they have voiced the need for a "mid-range" solution, featuring high-end functionality and performance in a cost effective package. The Xilinx® Kintex™-7 family of FPGAs was developed for these applications, delivering the most balanced power and performance in the industry while providing high-end features, such as cutting-edge transceivers, integrated IP, and extensive DSP resources.
While general-purpose graphics processing units (GP-GPUs) offer high rates of peak floating-point operations per second (FLOPs), FPGAs now offer competing levels of floating-point processing. Moreover, Altera® FPGAs now support OpenCL™, a leading programming language used with GPUs.
This white paper describes how to design an efficient polyphase and non-polyphase digital predistortion (DPD) feed-forward path solution with Altera® 28nm FPGAs, especially the Arria® V family of FPGAs. In addition, a resource usage and power comparison between different architectures is provided to facilitate design tradeoffs.
Today’s copper-based high-speed serial interfaces can deliver data at multi-gigabit rates. Data transfer rates exceeding 100 Gbps are possible by using multiple lanes in parallel, but are limited in the distance they can travel. One approach that improves the distance is to use optical interconnects rather than copper. Altera Corporation and Avago Technologies Inc. have jointly developed a solution that combines an FPGA and optical transmitter and receiver modules into a single integrated solution that can replace copper interconnects and multiple card-edge optical transceivers.
This paper describes key technologies that enable Stratix IV GT FPGAs to deliver the performance and capabilities necessary to support 40G/100G applications with integrated 11.3-Gbps transceivers. These include the LC-based oscillator and decision-feedback equalization (DFE) at 40 nm for ultra-low jitter FPGA transceivers. Furthermore, the transceiver architecture, including clocking and clock data recovery (CDR) technologies, are highlighted, as well as performance validation results.
Lower power consumption and higher bandwidth are the dominant requirements in designing next-generation high-end applications. The trend is for higher bandwidth in the same footprint at the same or lower power and cost as the Internet goes mobile. The march to 40G and 100G systems is underway to support this ever-growing bandwidth demand. Fierce competition is driving down prices. Space constraints abound, and cooling solutions often dominate the power budget, sometimes up to twice the power consumption of the electronics. Altera’s 28-nm FPGAs address these challenges through leading-edge technological innovation, integration, and reduced power consumption.
Lowest system power can be achieved by utilizing low-power FPGAs, which can be more power efficient than processors, ASSPs, and ASICs. When evaluating low-power FPGAs, key considerations include the power efficiency of the process technology, architectures and features, system interconnects, and EDA software. Altera® Cyclone® V FPGAs excel at all of the above metrics, and do so at the lowest system cost.
Altera® Cyclone® V FPGAs help designers reduce total system cost in a number of ways. Designers benefit not only from TSMC’s 28-nm Low Power (28LP) manufacturing process, but also from the architectural decisions that have gone into the Cyclone V device family and the array of powerful productivity-enhancing tools featured in Altera’s design tool ecosystem. With Cyclone V FPGAs, customers not only enjoy the lowest cost of ownership in the industry, but the widest array of low-cost parts available—from 25K logic elements (LE) to 301K LEs—and the only 28-nm solution under 100K LEs.
Over the past several years, Xilinx has been making a transition from the leading FPGA vendor to a provider of All Programmable Solutions for Smarter Systems. But just what do those words mean? It means that the FPGA fabric, the fundamental building
block of all Xilinx silicon products—All Programmable FPGAs, 3D ICs, and SoCs—has reached a critical threshold at the 28nm
process node. This threshold marks the transition where FPGAs have evolved to the point where they are large enough and fast
enough to implement complete systems. At 28nm, Xilinx is capable of replacing entire ASSPs and ASICs, which means that a
Xilinx All Programmable device equipped with the right IP and software may well be the only significant integrated circuit needed to implement many end products. Read the incontrovertible proof in this backgrounder.