As high-speed I/O (HSIO) and serial link data rates keep increasing, the requirements for accuracy and advanced simulation and modeling techniques get more stringent. This white paper reviews the techniques used in recent HSIO simulation and modeling, such as statistical behavioral, SPICE, and IBIS-AMI models, outlining the areas where they fall short in comparison with the emerging requirements. This paper also introduces Altera's JNEye transceiver link simulation tool and discusses how the tool enhances HSIO link modeling and simulation. This paper includes simulation and experimental results that demonstrate how the JNEye tool can meet the emerging requirements.
FPGA-based prototypes deliver high-performance operation and real-world connectivity but unless they can be brought-up and deployed early in the ASIC development project the speed and connectivity benefits are of no use if the prototype is late. Prototypes must be rapidly assembled and ASIC RTL “drops” integrated and made operational for validation scenarios and software integration in weeks – not months. With development cycles shrinking and software content growing, the demand for software-driven, in-context validation of new RTL blocks and IP requires that FPGA-based prototypes be delivered as fast as possible.
ASIC and SoC development projects demand prototypes as early as possible for system validation and hardware/software integration. A combination of a Design-for-Prototyping (DFP) methodology and automation tools can help design engineers responsible for emulation and prototyping to accelerate the time to first prototype and then replicate it successfully for distribution to other end-users like firmware/software developers.
Power integrity is a crucial part of successful design signoff. This paper discusses Voltus™IC Power Integrity Solution, a new tool that speeds power integrity analysis and signoff by 10X compared to other technology available, while still providing SPICE-like accuracy. The tool integrates with a full suite of design implementation and signoff tools, together overcoming signoff challenges to deliver the industry’s fastest design closure flow.
As old methods fall short, new techniques make advanced SoC verification possible. This paper presents mixed-signal block and IC-level verification methodologies using analog behavioral modeling and combined analog and digital solvers. It then describes analog real number modeling (RNM) and how it is used in top-level SoC verification.
The UltraScale™ architecture combines a successful architectural platform with numerous innovations and second-generation 3D IC technology to deliver breakthrough system performance, unprecedented capacity, and lower power. Based on the industry's first ASIC-class programmable architecture, Kintex® UltraScale and Virtex® UltraScale devices are enabling system OEMs to build smarter systems with fewer devices…faster. Read this white paper to learn more.
This white paper describes the tools, design flow, and verification of systems using Altera(r) FPGAs. It discusses the techniques of software simulation and hardware testing, and the challenges associated with them. This paper also describes the advantages of using the Hardware in the Loop (HIL) tool, which is part of Altera's software tools, to simplify software simulation and hardware testing in a variety of applications.
This white paper examines how Altera's optimized and verified intellectual property (IP) blocks can simplify your design, reduce design issues, and shorten time to market. It also explains how Altera's Generation 10 FPGAs enables broad portfolio of complex IP-the broadest portfolio in the industry-to achieve a 50 percent reduction in size while achieving twice the performance of current devices.
Advanced Driver Assistance Systems (ADAS) are the next wave of innovations to make driving on our more and more congested roads safer. This white paper discusses the use of Altera(r) FPGAs in safety-critical ADAS that have better performance requirements than commercial off-the-shelf (COTS) products. It looks at the general safety concept of such applications and provides examples on how to implement certain diagnostics in the FPGA to detect faults in the application.
SoC FPGAs are a powerful new class of programmable devices that are applicable to a wide range of electronic designs. This white paper discussed a number of criteria to select the best SoC FPGA for your particular application, including system performance, design reliability and flexibility, system cost, power consumption, future product roadmaps, and the important role that development tools will play into the success of these SoC FPGAs.