Traditional mixed-signal design environments, in which analog and digital parts are implemented separately, are no longer sufficient and lead to excess iteration and prolonged design cycle time. Modern mixed-signal designs require new flows that maximize productivity and facilitate close collaboration among analog and digital designers. This paper outlines mixed-signal implementation challenges and focuses on three advanced, highly integrated flows to meet those challenges.
To maximize your investment in EDA tools, your infrastructure and processes must be optimized for growing and frequently changing design needs. Cadence Client Technology Solutions is dedicated to enhancing EDA tool performance, ensuring stability, and removing critical bottlenecks. Through close collaboration with hundreds of customers worldwide, we have unique insight into environmental conditions and how best to maintain a high-performing design environment.
Power consumption has moved to the forefront of digital IC development as component sizes shrink and insulating layers on gates become thinner. To enable today’s advanced low-power techniques, the design flow must holistically address the architecture, design, verification, and implementation of low-power designs. Cadence offers the design, implementation, and verification tools and flows to address all areas of low-power design throughout the entire SoC development process.
In this episode of Chalk TalkHD Amelia chats with Greg Proehl (STMicroelectronics) about the basics of NFC technology, and they explore some interesting NFC applications as well as cool and innovative new NFC solutions from ST - including one with energy harvesting capability.
The SoC FPGA design is a new device that incorporates both FPGA and microcontroller subsystem on a single device. As these devices capabilities extend to high speed serial and DDR memory interfaces, and high performance FPGA fabric with DSP processing, the architecture within the device requires an advanced tool methodology to simplify the designer’s experience and accelerate time-to-market. System Builder accomplishes this by guiding users visually, presenting a high level abstraction for construction and then generating a “correct by construction” implementation of the system components.
IGLOO®2 devices have a range of differentiated security features, including a secure boot feature, which verifies that the boot code used to ‘bring-up’ an embedded system is authorized to run on the target processor. Without this check of the MCU, a malicious intruder can compromise the entire system. This paper outlines the dangers of poor system security and illustrates how implementing a secure boot can dramatically increase the security of embedded systems. It also shows how secure boot may be included for free, since IGLOO2 FPGAs are used to implement many common embedded functions other than security.
The 20nm process node represents a turning point for the electronics industry. While it brings tremendous power, performance and area advantages, it also comes with new challenges in such areas as lithography, variability, and complexity. The good news is that these become manageable challenges with 20nm-aware EDA tools when they are used within end-to-end, integrated design flows based on a “prevent, analyze, and optimize” methodology.
Transaction level modeling (TLM) is gaining favor over register-transfer level (RTL) for design components because of its many advantages—including faster design and verification times, easier IP reuse, and broader micro-architecture exploration. Cadence offers methodology guidelines, high-level synthesis, TLM-aware verification and debugging, and services to help designers combine new TLM IP with legacy RTL IP during this transition in design and verification environments.
Analog power has always been the standard. New digital power modules offer great flexibility, but that comes with a price. For many applications, we'd love to have the simplicity and efficiency of analog power with the features of digital power. In this episode of Chalk TalkHD Amelia Dalton chats with Steve Stella from Microchip Technology about mixing the best of digital and analog power.
It is critical that teams begin GLS as early in the design cycle as possible, that the simulator run in high-performance mode, and that a proven simulation methodology be in place. This white paper explores new simulator use models and methodologies that boost GLS productivity, including extraction via static timing analysis and linting. Using these approaches, designers can focus on verifying real gate-level issues rather than waste expensive simulation cycles on re-verifying working circuits.