For the engineer doing desktop PCB layout, efficiency is important. You don't want to waste precious time fighting with your PCB tool, and you don't want to end up with lousy results because you and your tool weren't getting along. Mentor Graphics PADS provides an efficient, high-productivity interactive placement and routing environment that lets you get great results quickly. In this episode of Chalk Talk, Amelia Dalton talks to Jim Martens of Mentor Graphics about interactive layout using PADS.
As high-speed I/O (HSIO) and serial link data rates keep increasing, the requirements for accuracy and advanced simulation and modeling techniques get more stringent. This white paper reviews the techniques used in recent HSIO simulation and modeling, such as statistical behavioral, SPICE, and IBIS-AMI models, outlining the areas where they fall short in comparison with the emerging requirements. This paper also introduces Altera's JNEye transceiver link simulation tool and discusses how the tool enhances HSIO link modeling and simulation. This paper includes simulation and experimental results that demonstrate how the JNEye tool can meet the emerging requirements.
FPGA-based prototypes deliver high-performance operation and real-world connectivity but unless they can be brought-up and deployed early in the ASIC development project the speed and connectivity benefits are of no use if the prototype is late. Prototypes must be rapidly assembled and ASIC RTL “drops” integrated and made operational for validation scenarios and software integration in weeks – not months. With development cycles shrinking and software content growing, the demand for software-driven, in-context validation of new RTL blocks and IP requires that FPGA-based prototypes be delivered as fast as possible.
ASIC and SoC development projects demand prototypes as early as possible for system validation and hardware/software integration. A combination of a Design-for-Prototyping (DFP) methodology and automation tools can help design engineers responsible for emulation and prototyping to accelerate the time to first prototype and then replicate it successfully for distribution to other end-users like firmware/software developers.
Learn how Vivado® IP Integrator can be used to rapidly connect a Zynq® processor to the programmable fabric. Using built in board aware design rule checks and designer automation, Vivado can greatly improve user productivity.
Power integrity is a crucial part of successful design signoff. This paper discusses Voltus™IC Power Integrity Solution, a new tool that speeds power integrity analysis and signoff by 10X compared to other technology available, while still providing SPICE-like accuracy. The tool integrates with a full suite of design implementation and signoff tools, together overcoming signoff challenges to deliver the industry’s fastest design closure flow.
As old methods fall short, new techniques make advanced SoC verification possible. This paper presents mixed-signal block and IC-level verification methodologies using analog behavioral modeling and combined analog and digital solvers. It then describes analog real number modeling (RNM) and how it is used in top-level SoC verification.
Xilinx showcases the industry’s first demonstration of a Kintex® UltraScale™ device with 16.3 Gbps backplane performance capability.
The UltraScale™ architecture combines a successful architectural platform with numerous innovations and second-generation 3D IC technology to deliver breakthrough system performance, unprecedented capacity, and lower power. Based on the industry's first ASIC-class programmable architecture, Kintex® UltraScale and Virtex® UltraScale devices are enabling system OEMs to build smarter systems with fewer devices…faster. Read this white paper to learn more.
Watch this video to learn how a complex SoC platform was mapped into a single Virtex®-7 2000T FPGA, the world's largest 3D IC in volume production. With well over 2 million logic cells, the Virtex-7 2000T reduces the need for design partitioning and simplifies the mapping of ASIC RTL. This breakthrough capacity coupled with Xilinx's Next Generation Vivado™ Design Suite provides the ideal solution to tackle the demands of leading edge ASIC and SoC devices.