A market leader in the Digital Home and Networking sectors, MIPS has adapted its industry-standard MIPS32® architecture to address the requirements of 32-bit microcontroller (MCU) product development, offering a higher-performance, more feature-rich and lower-power solution than that offered by competing cores based on the ARM® architecture. This paper outlines the design features that are implemented in MIPS® processor cores that contribute to their industry-leading performance. Additionally, we compare and contrast MCU design solutions based on the MIPS and ARM architectures. We will provide you with the substance beyond the hype, and key considerations for choosing a MIPS processor core.
Scaling processing performance beyond the frequency and power envelope of single core systems has led to the emergence of multi-core clusters. Data access management within such processing systems becomes essential to ensure behavioral consistency. One solution to provide access consistency is the application of a memory coherence model such as MESI or MOESI within the L1 data cache hierarchy. For the MIPS Technologies MIPS32® 1004K™ Coherent Processing System (CPS), we applied Open Core Protocol (OCP) point-to-point connectivity to establish snoop-based coherence throughout the cluster. Following are principles of this communication model.
Are you working on Android apps development? This app note on the MIPS NDK describes how to build Android applications in native C or C++.
Experience the SmartCE (Connected Entertainment) for Android platform from MIPS Technologies in this new video demonstration. The SmartCE Platform enables MIPS licensees and their customers to bring differentiated connected entertainment solutions to market quickly.
Software investment is the biggest ticket item in any project. Hence it is important to choose an instruction set architecture (ISA) that offers a truly scalable solution for future development. To address various embedded market segments, MIPS Technologies offers distinct, binary-compatible families of processor cores that span applications from 32-bit microcontrollers all the way to 64-bit multi-threaded, superscalar many-core processors for networking infrastructure, and numerous digital consumer markets in between. Since one can seamlessly scale the performance range between a wide array of processors, the MIPS® architecture offers an ideal path for protecting software investment on a new design or a follow-on/upgrade to an existing project. This paper illustrates the ease of migration from the Power to MIPS architecture, and highlights the areas that users need to focus on during this process.
Software investment is the biggest ticket item in any project. Hence the choice of an ISA that offers a scalable solution is an important consideration. MIPS and our SoC eco system offer distinct families of processor cores that span from 32-bit micro controllers all the way to 64-bit multi-threaded super-scalar cores from single-core to many cores, to address various segments of the embedded markets. For either a new design or a follow on or upgrade to an existing design, the choice of MIPS as the ISA offers an ideal path for protecting the software investment on a project, since one can scale the application up and down the performance scale seamlessly between a wide range of processors. The bulk of the effort in the migration to any new ISA is in the low-level initialization software. This paper illustrates the ease of migration from the ARM to MIPS architecture and highlight the areas that users need to focus on.
Google and partners recently announced Google TV—an open, architecture-neutral platform that will bring the full web experience to television viewing. Given the fact that MIPS licensees lead in the digital home today, it is likely that there will be a large number of future Google TV systems based on the MIPS architecture. Leveraging our work with Android and our ongoing relationship with Google, MIPS is in an excellent position to work with our licensees as Google TV moves beyond initial reference platforms and into mainstream development within the digital home market. By designing your SoC to the right specifications now, you can be ahead of the market when the Google TV code is available in open source in 2011. In this paper, we will provide you with an in-depth description of hardware requirements and recommendations for developing an SoC that will support the Google TV operating system!
Hardware-based multi-threading technology has for some time been known in the industry as a feasible technique for improving system performance, but not too many people are aware of just how much traction the technology has gained since its early implementations in the 1960s. This article provides a brief history of hardware based multi-threading and some examples of its commercial adoption so far. It then gives an overview of the fundamental value of multi-threading in hardware, and describes MIPS Technologies’ multi-threading architecture and product offerings. The article also provides several multi-threaded application examples—including those in the areas of driver assistance systems and home gateways—to demonstrate the broad applicability of multi-threading in real-world applications.