As high-speed I/O (HSIO) and serial link data rates keep increasing, the requirements for accuracy and advanced simulation and modeling techniques get more stringent. This white paper reviews the techniques used in recent HSIO simulation and modeling, such as statistical behavioral, SPICE, and IBIS-AMI models, outlining the areas where they fall short in comparison with the emerging requirements. This paper also introduces Altera's JNEye transceiver link simulation tool and discusses how the tool enhances HSIO link modeling and simulation. This paper includes simulation and experimental results that demonstrate how the JNEye tool can meet the emerging requirements.
This white paper describes the tools, design flow, and verification of systems using Altera(r) FPGAs. It discusses the techniques of software simulation and hardware testing, and the challenges associated with them. This paper also describes the advantages of using the Hardware in the Loop (HIL) tool, which is part of Altera's software tools, to simplify software simulation and hardware testing in a variety of applications.
This white paper examines how Altera's optimized and verified intellectual property (IP) blocks can simplify your design, reduce design issues, and shorten time to market. It also explains how Altera's Generation 10 FPGAs enables broad portfolio of complex IP-the broadest portfolio in the industry-to achieve a 50 percent reduction in size while achieving twice the performance of current devices.
Advanced Driver Assistance Systems (ADAS) are the next wave of innovations to make driving on our more and more congested roads safer. This white paper discusses the use of Altera(r) FPGAs in safety-critical ADAS that have better performance requirements than commercial off-the-shelf (COTS) products. It looks at the general safety concept of such applications and provides examples on how to implement certain diagnostics in the FPGA to detect faults in the application.
SoC FPGAs are a powerful new class of programmable devices that are applicable to a wide range of electronic designs. This white paper discussed a number of criteria to select the best SoC FPGA for your particular application, including system performance, design reliability and flexibility, system cost, power consumption, future product roadmaps, and the important role that development tools will play into the success of these SoC FPGAs.
Intellectual property (IP) is a key component in system designs for many different end markets. This white paper explores how Altera and partner IP solutions can provide the differentiation you need for your next-generation applications. This white paper examines the feasibility of developing IP in-house or buying from a third party, and also presents Altera's innovative IP scalability, integration, and delivery model. With this model, Altera not only simplifies the process of acquiring, evaluating, testing, and integrating IP into your design, but also mitigates the risks of using third-party IP.
This is a joint paper by ARADEX and Altera, which examines the advantages of using FPGA technology in high-precision servo drives compared to standard solutions based on microcontrollers or digital signal processors (DSPs). This paper also describes Altera's FPGA capability to execute many processes in parallel for complex systems without increasing the cycle time.
FPGAs are increasingly replacing electronic components used for industrial applications, thus international standards like the IEC 61508 have to support these evolving technology trends if they want to keep their relevance. This white paper gives developers eight simple reasons why FPGAs should be chosen in their IEC 61508 functional safety project versus standard microcontrollers or DSPs.
A product strategy that uses a tailored approach drawing upon using different process technologies, architectures, and integration options targeted to different applications will give hardware architects the best possible choices and solutions. This white paper covers examples of why telecommunication bandwidth and the infrastructure behind it is driving FPGA capabilities, business challenges of ASICs and ASSPs, and how a tailored approach for programmable logic devices (PLDs) provide a leap in FPGA capabilities. This paper also outlines Altera’s generation 10 portfolio of next-generation FPGAs and SoCs that seeks to provide a breakthrough in capabilities and advantages across a variety of different applications.
Today’s Information and Communications Technology (ICT) equipment developers face a daunting problem in addressing exponential growth in bandwidth demand while minimizing power consumption. This white paper outlines the performance and power requirements for next-generation programmable logic solutions to meet the demands of the growing ICT sector by leveraging multiple process technologies and revolutionary approaches to transistor design, new architectures, and comprehensive device-level power features.