Learn how Vivado® IP Integrator can be used to rapidly connect a Zynq® processor to the programmable fabric. Using built in board aware design rule checks and designer automation, Vivado can greatly improve user productivity.
Xilinx showcases the industry’s first demonstration of a Kintex® UltraScale™ device with 16.3 Gbps backplane performance capability.
The UltraScale™ architecture combines a successful architectural platform with numerous innovations and second-generation 3D IC technology to deliver breakthrough system performance, unprecedented capacity, and lower power. Based on the industry's first ASIC-class programmable architecture, Kintex® UltraScale and Virtex® UltraScale devices are enabling system OEMs to build smarter systems with fewer devices…faster. Read this white paper to learn more.
Watch this video to learn how a complex SoC platform was mapped into a single Virtex®-7 2000T FPGA, the world's largest 3D IC in volume production. With well over 2 million logic cells, the Virtex-7 2000T reduces the need for design partitioning and simplifies the mapping of ASIC RTL. This breakthrough capacity coupled with Xilinx's Next Generation Vivado™ Design Suite provides the ideal solution to tackle the demands of leading edge ASIC and SoC devices.
This video demonstrates the world's first all programmable heterogeneous FPGA interfacing to a CFP2 Optical Module. The demo walks through 4 steps required to bring up the system and then shows how Xilinx simplifies the integration process.
Many designers either don’t have the equipment to debug an FPGA serial link or when they do, they don’t get much information by physically probing traces on the board. Using PCI-Express as an example, this demonstration will show how to perform system margin analysis during live signal transmission without interrupting data flow.
Systems with high speed serial links often have serial channels which result in signal distortion described as insertion loss, reflection, cross-talk, and other channel impairments. Receiver equalization can help compensate for such channel-driven losses and distortions, but link tuning and bring-up can be non-trivial even for the most experienced transceiver and signal integrity specialists. Learn how Xilinx FPGAs with fully auto-adaptive equalization is critical to high speed transceiver design and enables system designers to get their systems up and running quickly.
Learn how Vivado® IP Integrator can be used to rapidly configure a Zynq® processor and connect it via AXI4 to a video accelerator running in the programmable fabric of the device. Using built in board aware design rule checks and designer automation, Vivado can greatly improve user productivity.
Learn how to access new place and route algorithms that you can try when the defaults do not meet your design goals. This covers the new command directives and the new pre-packaged strategies that are built on these directives.
7 series FPGA GTH transceivers have achieved 100% electrical conformance to the 10GBASE-KR standard. In this video you'll see a Virtex®-7 FPGA pass the specification's receiver interference tolerance test over a 24" backplane.