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Power Supply Management in High-Availability Systems
One of the most basic (and most often overlooked) aspects of high-reliability system design is getting reliable power to all of our components. We need the right kind of power at the right places - at the right times, and in the right order. We need to handle power-up, power-down, and reset cases (among others). It can be really complicated. In this episode of Chalk TalkHD, Amelia Dalton chats with Wendy Lockhart of Microsemi about how to handle power management for high-reliability systems.
Chalk Talk sponsored by Microsemi
FPGA Prototyping with the Kintex-7 KC705 Evaluation Kit
In this episode of Chalk Talk HD, Amelia chats with Evan Leal of Xilinx about their new Kintex-7 KC705 Evaluation Kit, all the cool stuff that’s included and how we can use it to speed up our FPGA Prototyping.
Chalk Talk sponsored by Xilinx
Choice of an ISA for Embedded Designs
Software investment is the biggest ticket item in any project. Hence the choice of an ISA that offers a scalable solution is an important consideration. MIPS and our SoC eco system offer distinct families of processor cores that span from 32-bit micro controllers all the way to 64-bit multi-threaded super-scalar cores from single-core to many cores, to address various segments of the embedded markets. For either a new design or a follow on or upgrade to an existing design, the choice of MIPS as the ISA offers an ideal path for protecting the software investment on a project, since one can scale the application up and down the performance scale seamlessly between a wide range of processors. The bulk of the effort in the migration to any new ISA is in the low-level initialization software. This paper illustrates the ease of migration from the ARM to MIPS architecture and highlight the areas that users need to focus on.
White Paper sponsored by MIPS
Embedded Signal Processing Capabilities of the LatticeECP3 sysDSP Block
To address these emerging needs, Lattice Semiconductor has continued its tradition of providing high performance DSP capabilities in its most recent low-cost, SERDES-capable LatticeECP3 FPGA family. Features such as a dual slice architecture, the ability to cascade/chain DSP slices and blocks and an enhanced instruction set establish the LatticeECP3 family as a compelling alternative for signal processing applications such as FIR filtering and FFT/iFFT implementations.
White Paper sponsored by Lattice
Tips and Techniques for 28-nm Design Optimization
Timing closure is of critical importance in high-speed FPGA designs. This white paper focuses on the challenges that affect timing closure and discusses how simple HDL changes can help resolve timing issues and reduce the time needed to achieve timing closure.
White Paper sponsored by Altera
Maximize Design Productivity With PCIe/104 FPGA/Processor
In this episode of Chalk TalkHD Amelia chats with Christine Van De Graaf of Kontron, who explain how Kontron is incorporating pre-made, small form factor boards, a high-performance embedded processor programmable logic into their new MSMST board and how we can get started designing with one.
Chalk Talk sponsored by Kontron
GEN2 Serial RapidIO and Low Cost, Low Power FPGAs
System designers will continue to be under pressure to produce higher performance systems yet maintain lower build and operational costs. DSP and Network Processing Unit (NPU) devices, coupled with low cost, low power FPGAs like the Lattice ECP3 that support Gen2 Serial RapidIO (SRIO), can provide an ideal platform for meeting these challenges.
White Paper sponsored by Lattice
Is Your Memory Design Correct and Reliable?
Learn how quickly and easily you can run a comprehensive memory test and uncover design and reliability issues. In this video, a memory failure is detected only in "burst" mode, while passing all other tests. A second development board passes all the tests.
Achieving Lowest System Cost with Midrange 28 nm FPGAs
Increased capability does not have to increase your cost. Arria V FPGAs provide the highest bandwidth and the most hard IP at the lowest price. In addition, by designing with Arria V FPGAs, you can save system costs, operating costs, and manufacturing costs.
White Paper sponsored by Altera
IP and Process Solutions for Energy-efficient PMICs
In this episode of Chalk TalkHD Amelia chats with Ravi Mahatme from ARM and King Ou from GLOBALFOUNDRIES about how IP and process solutions can help solve our power management problems.
Chalk Talk sponsored by ARM
chalk talks
Spartan-6 FPGAs in Video Designs
In this episode of Chalk TalkHD, Amelia chats with Tom Hill and Maureen Smerdon of Xilinx about how Spartan-6 FPGAs can accelerate your next video design, and how adding embedded vision to those designs is getting easier and easier.
Chalk Talk sponsored by Xilinx
Scalable Smart Debugging With ZeBu-Server
In this episode of Chalk TalkHD, Amelia chats with Lauro Rizzatti of EVE about how EVE's ZeBu emulation technology can help you find that one last bug in even the biggest of designs.
Chalk Talk sponsored by EvE
Hierarchical Design Flows: Design Preservation & Team Design
In this episode of Chalk TalkHD, Amelia chats with David Dye of Xilinx about how Hierarchical Design methodologies and Team Design can accelerate your next FPGA design and get those team members of yours working productively together. With these tools and techniques, two million logic elements won't seem like that much after all.
Chalk Talk sponsored by Xilinx
Adding Wi-Fi to Your FPGA Design
In the first episode of our new Chalk TalkHD series, Amelia Dalton talks to Bob Potock from Altium as they add Wi-Fi to an FPGA-based embedded system.
Chalk Talk sponsored by Altium
Intel Atom™ Processor with built-in Altera Arria® FPGA
In this Chalk TalkHD Amelia talks to David Schmidt of Arrow about the new Intel Atom™ processor with an Altera Arria FPGA built right into the package.
Chalk Talk sponsored by Arrow
IP and Process Solutions for Energy-efficient PMICs
In this episode of Chalk TalkHD Amelia chats with Ravi Mahatme from ARM and King Ou from GLOBALFOUNDRIES about how IP and process solutions can help solve our power management problems.
Chalk Talk sponsored by ARM
latest papers and content
FPGA Prototyping with the Kintex-7 KC705 Evaluation Kit
In this episode of Chalk Talk HD, Amelia chats with Evan Leal of Xilinx about their new Kintex-7 KC705 Evaluation Kit, all the cool stuff that’s included and how we can use it to speed up our FPGA Prototyping.
Chalk Talk sponsored by Xilinx
It's 2022: Do You Know What Your FPGA Is?
Does the definition of "FPGA" seem like a moving target? Over the past few years, there has been phenomenal progress in FPGA technology - going from simple glue logic to impressive programmable systems-on-chip. Today's FPGAs are some of the most powerful and flexible devices ever built. But, what will your FPGA look like ten years from now? In this episode of Chalk TalkHD, Amelia Dalton chats with Umar Mughal of Altera about the past, present, and future of this exciting technology.
Chalk Talk sponsored by Altera
Is Your Memory Design Correct and Reliable?
Learn how quickly and easily you can run a comprehensive memory test and uncover design and reliability issues. In this video, a memory failure is detected only in "burst" mode, while passing all other tests. A second development board passes all the tests.
Embedded Design Verification Best Practices Short Video
Watch this short video on Embedded Design Verification Best Practices and learn how to verify embedded designs for correctness and reliability utilizing a NEW approach employing a Verification and Test OS (VTOS™).
Troubleshooting and Fast Fault Isolation with VTOS
Troubleshooting and quickly isolating faults is of tremendous value for reducing the time to redesign or repair failing boards. This process can cost a company millions of dollars each year. Supporting OMAP, Sitara, QorIQ, PowerQUICC and PowerPC, this paper describes how using an interpreter that allows the execution of a full test suite for verifying a design or an individual test for fault isolation can dramatically improve quality and reliability with Kozio’s Verification and Test OS (VTOS™). It describes how memory errors can be isolated to ECC (Error Control Coding), single-bit, row, column, and correlated to a part’s reference designator.
Sponsored by: Kozio
A Platform for Reducing Verification Time and Improving Reliability of Embedded System Hardware
In this whitepaper the author reviews how leveraging VTOS during the prototype phase can assist engineers in overcoming the challenges design complexity exerts on product development, manufacturing, and overall time-to-market. Readers will gain insight into how they can replace today’s ad-hoc board level verification approaches with an ordered methodology that enables designers to automatically validate their own hardware designs, optimize system performance, and simplify the process of integrating new hardware with new software.
White Paper sponsored by Kozio
Memory Testing 101 – Avoid the Train Wreck
Memory is fundamental to the “sanity” of an embedded system. Inadequate memory testing is posing critical challenges to designers and indirectly manifesting considerable consequences at some of the biggest names in the electronics business. Today’s embedded systems consist of multiple memory types including SDRAM, LPDDR2, DDR3, FLASH, EEPROM and more, along with multiple protocols including GPIO, PCI, SPI and I2C. This paper will review a comprehensive and flexible Verification and Test Operating System (VTOS™) solution that includes a suite of memory tests that verifies the design for correctness and production readiness.
White Paper sponsored by Kozio
Customer Private Label Program
Customers have prototyped their products utilizing Microsemi FPGA & cSoCs and then quickly went to production on the same platform. This ensures design consistency and gets product to their customers on time as scheduled. Microsemi’s private label program goes a step further and provides the ability to custom mark devices with company logo’s and part numbers. Furthermore, our devices do not require an external EEPROM for boot-up configuration, thus the end product can be sold as single IC solution. This approach provides numerous levels of security including prevention of reverse engineering coupled with 128-bit encryption keys to unlock and reprogram your device for field upgradability when the need arises.
System Management
Semiconductor devices are prone to failure even after they have been tested, packaged and shipped by the semiconductor vendor. The main factors that contribute to device failure in a system are electrically, environmentally and mechanically induced failures. Because mechanical failures are almost impossible to mitigate at the electrical or electronic design stage the following discussion focuses on electrical and environmental stresses.
Sponsored by: Microsemi
Power Supply Management in High-Availability Systems
One of the most basic (and most often overlooked) aspects of high-reliability system design is getting reliable power to all of our components. We need the right kind of power at the right places - at the right times, and in the right order. We need to handle power-up, power-down, and reset cases (among others). It can be really complicated. In this episode of Chalk TalkHD, Amelia Dalton chats with Wendy Lockhart of Microsemi about how to handle power management for high-reliability systems.
Chalk Talk sponsored by Microsemi
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Memory Testing 101 – Avoid the Train Wreck
Memory is fundamental to the “sanity” of an embedded system. Inadequate memory testing is posing critical challenges to designers and indirectly manifesting considerable consequences at some of the biggest names in the electronics business. Today’s embedded systems consist of multiple memory types including SDRAM, LPDDR2, DDR3, FLASH, EEPROM and more, along with multiple protocols including GPIO, PCI, SPI and I2C. This paper will review a comprehensive and flexible Verification and Test Operating System (VTOS™) solution that includes a suite of memory tests that verifies the design for correctness and production readiness.
White Paper sponsored by Kozio
Innovating With a Full Spectrum of 40-nm FPGAs and ASICs With Transceivers
Increasing bandwidth requirements for broadband services are driving silicon vendors to use more and more high-speed serial transceivers. Therefore, next-generation applications feature a wide range of data rates, from a few Mbps to hundreds of Gbps, and integrate multiple protocols and services in a single box. This paper describes how 40-nm FPGAs and ASICs with transceivers address these challenges by leveraging the advantages of leading-edge technology and reusing previous innovations.
White Paper sponsored by Altera
Fulfilling Technology Needs for 40G–100G Network-Centric Operations and Warfare
The development and deployment of network-centric operations and warfare (NCOW) to integrate and connect the military’s many separate networks relies on high-speed packet transport and optical networking. Altera’s 28-nm Stratix® V FPGAs combine the flexibility needed to adapt to changing network standards and support legacy network interfaces and protocols, while offering the ASIC-like performance traditionally required for these applications. This unprecedented combination of technological advances enables advanced network developers to implement and deploy military capabilities in a secure and flexible manner while dramatically reducing NRE and critical time to mission.
White Paper sponsored by Altera
Dynamic Power Reduction in Flash FPGAs
Due to the dramatic increase in portable and battery-operated applications, lower power consumption has become a necessity in order to prolong battery life. Power consumption is an important part of the equation determining the end product's size, weight, and efficiency. FPGAs are becoming more attractive for these applications due to their shorter product life cycle.
The What, Why and How of Customizable Dataplane Processors (DPUs)
There are a lot of data-intensive functions that control processors cannot handle. That’s why designers turn to RTL. However, RTL blocks take a long time to design and even longer to verify. Dataplane processors (DPUs) are designed to provide programmability in the performance-intensive dataplane of the SOC design. You can think of them as a combination of a DSP and a CPU – but they’re even better than that, as you can customize them for maximum efficiency for your target application. Need wide datapaths or instructions? You need a DPU.
White Paper sponsored by Tensilica
A Review of BCDlite
GLOBALFOUNDRIES offers BCDliteTM foundry technology optimized for applications such as power management devices, audio amplifiers, displays and LED driver integrated circuits (ICs).
Data Sheet sponsored by ARM
Six Ways to Replace a Microcontroller With a CPLD
With the advent of low-power CPLDs, low-power electronic product designers now have new options for implementing many of the functions traditionally performed by microcontrollers. This white paper discusses when it is advantageous to use a CPLD instead of a microcontroller, and when it makes sense to use a CPLD as a companion to a microcontroller, with examples grouped into three categories—I/O management, port management, and system management—based on their function and level of complexity.
White Paper sponsored by Altera
Embedded Signal Processing Capabilities of the LatticeECP3 sysDSP Block
Field programmable devices are continually being adopted in new market segments, where they are being implemented as mainstream logic devices. These new market segments are increasingly driving competing FPGA vendors to incorporate a wider variety of functionality and flexibility within their devices. Embedded digital signal processing (DSP) is one such function, addressing a wide gamut of market segments.
White Paper sponsored by Lattice