June 30, 2009 - IP has gone from wishful thinking to a real business and an integral part of the IC design process. But if the teeth-gnashing and pain of several years ago were still relevant, it would be hard to imagine how IP could really be providing value. The fact that people do seem to use it would suggest things are more manageable now. This week we take a look at IP use in ICs. In fact, it’s the first of three articles spawned by this topic (the other two of which will show up over the next couple months).

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Bryon Moyer - Editor
IC Design and Verification Journal

IP Inexact
A Look at Life in the IP World
(Bryon Moyer)

Intellectual property (IP) is, in our modern edition of the SoC design world, the equivalent of the opposite gender (in our modern equal-opportunity-exasperation world): you can’t live with it and you can’t live without it. The thought of bundling up the results of some great achievement to share with your peers (or better yet, superiors?) was once a nice thought, something to do if you had some time. You could even spare someone a bunch of work that way. Or, if you were lucky, actually sell it.

There are, of course, a couple of problems with that theory. First of all, you never have time. But then, even if you did, once you put your grand oevre out for others to admire, nay, worship, you expect the congratulatory emails to come streaming in. But as the first one arrives and you eagerly open it, you find: there’s a problem, something isn’t working, can you please help figure out what’s wrong.

[Cue sound of massive ego deflation.]

The reality of reusing IP was a massive wet blanket that all but doused the struggling embers for years. But the fire was never put out, partly because, as much of a pain in the backside as it can be, IP isn’t a nicety anymore. You can’t waste time reinventing things that have already been reinvented. And the pressure is such that “I can do it better” ego trips are being deferred like that long sought-after vacation. [more]

Working Towards Independence
CriticalBlue Tries to Assist Parallelization
(Bryon Moyer)

Everyone’s trying to make their code run faster. Since we can’t count on processors simply doing the work for us by running faster, we have to resort to other means. For code that’s going to run on SoCs, there are a couple primary choices: add more cores and have them run in parallel or have some of the code execute in dedicated hardware.

The whole parallel thing has been bandied about for years now, and no one has found a way around the fact that it’s really hard to take a serial programming paradigm and create a parallel implementation. Meanwhile, there are a number of solutions for creating hardware accelerators, although a quick sample of users suggests that most such tools yield less than overwhelming results. [more]

Executive Profile: Rajeev Madhavan
(Bryon Moyer)

You never know with CEOs these days. There was a time when there was a certain order to things, a level of formality. CEOs would set themselves apart, and, in emulation of that, so would their teams. Mahogany Row represented the corporate pantheon, and veneration was the expected order of the day. Fallibility would be, if not brushed off outright as beyond possibility, at least not broached. We’ve probably all known some old-school CEOs. The ones you can’t speak to unless spoken to first. The ones that like to keep their execs guessing what it is they want. The ones that are all stick, no carrot. The ones that change the rules frequently and arbitrarily so that no one gets too comfy.

But these days, well, you just never know. Heading into a conversation with Magma’s Rajeev Madhavan, I wasn’t sure what to expect. I had met him only briefly as he prepared for his MUSIC keynote speech a couple months ago. At that time, like anyone, he was preparing to go on stage, and so, while congenial, his mind and style were focused on the upcoming presentation. Not necessarily representative of what his day-to-day style might be. [more]

Skew This!
Azuro Touts Clock Concurrent Optimization for Aggressive Nodes
(Bryon Moyer)

The concept of clocking a register is pretty simple. It’s Logic Design 101 stuff. Having an entire system controlled by a uniform clock makes accessible that which would otherwise be an intractable problem. It’s like adding traffic lights downtown to keep traffic from getting completely chaotic.

A whole discipline has grown out of this very basic concept: that of synchronous design. An entire ecosystem of tools and techniques has been built around some very fundamental assumptions of how to design such circuits. And as the circuits have gotten bigger, clock tree synthesis (CTS) has become an art in its own right. But, according to the team at Azuro, the foundation on which it’s built has some cracks in it, and that foundation needs to be replaced. [more]

Dueling DFMs
Mentor and Synopsys Announce DFM Developments
(Bryon Moyer)

Design For Manufacturing (DFM) was a headline darling for a while and somehow disappeared off the radar, even as debates continued as to whether all the DFM fuss was about nothing. In fact, much of what constitutes DFM, originally implemented as point tools by young upstart companies, has quietly been subsumed into mainstream flows by mainstream tool providers, thanks in part to the traditional EDA start-up/buy-up cycle.

Fundamentally, design and verification have gone from modeling the idealized results of a manufacturing process to modeling the actual manufacturing steps in much greater detail. The criticality and accuracy required have evolved so that what was once a conceptual shift, moving manufacturing considerations into the design sphere, have now become standard, and the tools are now on that general trend of increasing precision and performance. [more]

Visibility Enhancement Technology Confronts the Visibility Issue with Full-Chip Simulation
by Martin Rowe, SpringSoft, Inc.

When it comes to system-on-chip verification, two trends have become painfully obvious: it is expensive and it takes too long. Consider, for example, that the most expensive parts of today’s SoC design flow are the tasks where the engineer must engage in direct manual effort or expend energy making decisions. In the case of verification, far too much time and money are wasted on tasks that don’t add value, such as trying to figure out how supposedly-correct intellectual property (IP) is actually working, debugging “dumb” errors or deciding what signals to record in any given simulation run. While improved design tools and methodologies, coupled with higher levels of abstraction, have made some headway in shortening design and verification times, the time required to determine the root cause of problems found in large, long simulations is growing. [more]

A Nice DATE in Nice
(Dick Selwood)

I have to confess a weakness – I love trade shows/exhibitions. I enjoy being involved in designing, creating and setting up trade show booths, enjoy working on a booth and talking to new people, and enjoy walking the aisles and learning about new products and new companies, particularly at a crowded show where there is a special buzz. I believe that, when properly used, they are an efficient weapon in the promotional arsenal and can easily repay the investment by the exhibitors and that, when properly used, they are an efficient way of adding to professional knowledge and expertise. Yet, apart from Germany (and, I am told, Japan), trade shows are becoming less and less popular. [more]

Demonstrating Targeted ROI
Key to Meaningful EDA Business Partnerships
by Holly Stump, Jasper Design Automation

Wall Street says, “Flat is the New Up!” GSA says, “Semiconductor sales for 2008 totaled $252 billion and dropped 6%, compared to 2007 sales of $268 billion.” California's unemployment rate hit a record 11.2 percent in March 2009, allegedly the worst since the Great Depression! In our own world, EE Times reports: “The unemployment rate for all engineers jumped from 2.9 percent in the fourth quarter of 2008 to 3.9 percent in the first quarter of 2009, IEEE said.” And Nostradamus predicted the end of the world… For businesses, it’s all about increasing productivity, maximizing ROI, accelerating time to market, and reducing risk. The stakes are higher than ever in this economy.  [more]