July 22, 2008 - This week we continue our look at Logic NVM. In a prior article we looked at one-time programmable (OTP) and multiple-time programmable (MTP) technologies. This time we look at some approaches that fall somewhere in the middle. When this article was conceived, they were provided by different companies... Typical of the fast- paced Silicon Valley style, where it's dangerous to blink, they are now under the same roof.

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Bryon Moyer – Editor
Techfocus Media, Inc.

A Non-Volatile Middle Ground
Few-Times-Programmable Memory from Virage and… um… Virage
(Bryon Moyer)

A few weeks ago we started a look at Logic Non-Volatile Memory (Logic NVM) options. These are non-volatile memories intended for embedding in SoCs using only standard logic processes instead of the more complicated processes designed to optimize large quantities of memory. We looked at one-time programmable (OTP) versions, which, not too surprisingly, can be programmed only once. We also looked at multiple-time programmable (MTP) versions, which can in general be programmed 100,000+ times while maintaining a data retention time of 10 years or more even on the 100,000th programming.

But there’s another flavor – or category with a couple flavors – that lies in between OTP and MTP, called few-times programmable (FTP). This is intended for applications where you really want to be able to make changes, but you’re not going to need to do it tons of times. One obvious such application is for code that may need to be patched. Unless you’re way out of control, you’re not going to need to patch your code 100,000 times. FTP memories can generally be programmed 10s to 100s of times; the limiting factor may be technology, or it may be architecture, depending on how the memory is implemented.

Conceptually, there are two ways to approach the problem. I should state here that, commercially, “FTP” may not be used to describe both of these, but I’m going to do so – more on that later. One approach is to make changes to the cell such that for a size benefit, you trade off the 100,000-cycle endurance. The other is to make architectural modifications to allow some “redos.” One obvious – if inefficient – way to do the latter is just to have several OTP memories that all look the same, along with a demux/mux pair on the input and output (and some way of configuring the demux/mux on power-up, either with a non-volatile cell or a configuration stored in external memory). If there are, say, four memories, then you start with the first one, program it, and, if you need to make a change, you use the second one instead and configure the demux to access not the first but the second and the mux to route not the first one’s outputs, but the second one’s. [more]

Yet Another Twist on Making Software Faster
CriticalBlue Creates Custom Coprocessors
(Bryon Moyer)

We seem to have this love/hate relationship with software. We like it because it’s so durn flexible and we can implement changes quickly. Well, unless we really hose things up. But you have to be a real goober to need a change that takes longer than a hardware change*. I mean a real hardware change, like a silicon spin.

But there’s a problem with software: it’s slow. Since the dawn of time, man has labored to find ways to make software go faster. OK, so maybe more like the dawn of Timex, but whatever, for a long time. Some of that effort has been on making software execute more efficiently through better coding and better-tuned processors. But another avenue pursued has been that of using hardware to make software faster, and this has taken a number of forms.

One of the earliest was the dedicated coprocessor – essentially a specialized microprocessor that did a few things very fast, like floating point math. These are still found in computers today for handling graphics, disk access, and other such peripheral tasks, but the coupling has decreased, meaning that the processor can hand things off and assume the job will get done right without much supervision. [more]

New Approaches to Long-Term Memory
A Quick Look at Logic NVM – OTP and MTP
(Bryon Moyer)

There’s been a quiet development brewing that you could file under “W” for “What’s old is new.” Non-volatile memory (NVM) is seeing renewed attention as Logic NVM, but with a twist – gone is the requirement for a boutique process. There’s enough activity here to warrant a one-day self-titled convention specifically dedicated to developments and usage (and particularly, quality and reliability). But I’m getting ahead of myself. To understand what’s new, we must understand what’s old.

There have essentially been three fundamental non-volatile technologies that have sold anything substantial. The oldest, metal fuses, has long since disappeared from mainstream (if not all) usage. The two that remain are floating-gate and anti-fuse. Floating gates are disconnected pieces of conductor; a controlled amount of charge is transferred to or from them, typically by either hot-electron injection or Fowler-Nordheim tunneling; anti-fuses are created by rupturing oxide, either between two layers of metal or between metal and poly or silicon. [more]

Fight! Fight! Please?
Trying to Start a War Between SystemC and SystemVerilog (Bryon Moyer)

Everyone loves a good fight. Peace? Harmony? Teach the world to sing? Bah! That’s hippie talk! There’s no excitement (or money) in that! Drama, now that’s what we want! (Some of us even want our own drama, but that’s a separate topic.)

OK, so when it comes to tech, perhaps the drama is less, well, compelling. Yes, we can snicker and leer self-righteously, but when we hold our grandkids in the thrall of stories about how things used to be back when we used wires, I’m not sure we’ll keep their attention with rollicking tales of the wars between CPF and UPF, or of legendary rivalries like AMD vs. Intel or Altera vs. Xilinx. So at this point it’s probably fair to start ratcheting back expectations a little; I’ll ask that your pulses diminish ever so slightly, that you ease your bottoms back away from the edge of your seats, where I know they’re positioned with great anticipation. [more]

Going Back to the Formal
Property Checking Puts a New Shine on Formal Verification
(Bryon Moyer)

Back a decade or so ago, there was a big hoo-hah about “formal verification.” Things burned hot for a while, then cooled down and more or less slipped away from view for most of us. And some of us may have been left with the impression that it was a good idea, perhaps, theoretically, but that practical realities got in the way of it being broadly useful. Now suddenly formal verification is getting some attention again. Which raises the question, what’s changed? [more]

Faster Space Exploration
Infiniscale Uses Behavioral Modeling to Design for Analog Yield
(Bryon Moyer)

In yet another installment of how life has gotten complicated in the design-for-manufacturing (or design-for-yield) world, we re-enter the world of the modern designer as contrasted from those of yore. Erstwhile designers followed rules, and, assuming the designs passed their tests on the way from design to manufacturing, the designer could give him- or herself a well-deserved pat on the back, release a satisfied sigh, and move on to the next project. What happened to the design at that point was not of concern to the design engineer because the design had escaped the realm of design. Testing was handled by test engineers, and yield enhancement was handled by – you guessed it -- yield enhancement engineers. [more]

Broken Design Flows and Point Tools
(Dick Selwood)

Where do you go for help when your design flow is broken? Wally Rhines of Mentor Graphics wants it to be to him and his company. He feels that the EDA tool chain breaks every 2.5 process nodes (and has some convincing PowerPoint slides to back his case), and that 45 nanometre is the next inflexion point.

Stemming from this he argued, when giving a Globalpress Electronics Summit Keynote, it takes a broken tool chain to get engineers to adopt new tools. And who can blame them? Apart from the cost of purchase, it is hard work changing to a new design tool. You have to learn not just how to use the tool but also how to use it to take advantage of short cuts, building on the tool’s strengths and working round the weaknesses, all the things you already know how to do with your existing tools. [more]

Sticking to Plan
Javelin and Magma Move Floorplanning Towards Production
(Bryon Moyer)

Floorplanning has become an important step in SoC design because it lets designers and managers get an early sense of what can be accomplished on a given piece of silicon. This is, of course, critical during the never-ending negotiation between design and marketing as to who’s on drugs and who’s sandbagging. It’s more or less the equivalent of doing furniture planning, where you draw a picture of a room and cut out rough scale versions of the furniture and move them around to get a rough sense of what will fit. Not particularly accurate, certainly not good enough for production, but much better than those back-of-the-envelope calculations that get more and more ambitious with every beer.
[more]

Trans-Acting Lessons
Modeling and Transactors for the Simulation and Emulation World (Bryon Moyer)

It is not a notable occurrence for me to find myself confused at any given moment on any given topic. However, finding that I’m not the only one confused – well, that pretty much makes it a red-letter day. Within the world of SoC verification, there are numerous points of potential confusion, and I’m finding much satisfying solidarity with other folks trying to navigate the space. [more]

Ten-Step Program
Sequence PowerArtist Identifies Ways to Reduce Power (Bryon Moyer)

Power has become a key design consideration for SoCs in pretty much any application. We’ve looked at some ways of reducing power in past articles, largely at a high level. We continue here with a specific look at some techniques that can be identified by a new tool from Sequence called PowerArtist. This tool takes ten specific steps to identify ways to reduce power, although only a couple of them are automatically implemented. Most of them may take some engineering evaluation to decide whether to implement, and, if so, exactly how to do them, so those techniques are so-called “guided” ones, in that the tool guides the engineer towards power savings opportunities. [more]